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SI6423DQ-T1-GE3

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Vishay Intertech MOSFETs, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI6423DQ-T1-GE3

Vishay Intertech · MOSFETs · TSSOP-8

SI6423DQ-T1-GE3 from Vishay Intertech, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D passive Drain of the P-channel MOSFET, rated for VDS = -12 V; pins 1, 5 and 8 are the drain and are connected together on the board.
2 S passive Source of the MOSFET; must be tied common with pins 3, 6 and 7.
3 S passive Source of the MOSFET; must be tied common with pins 2, 6 and 7.
4 G input Gate of the P-channel MOSFET; gate-source voltage limited to ±8 V.
5 D passive Drain of the P-channel MOSFET, connected together with pins 1 and 8.
6 S passive Source of the MOSFET; must be tied common with pins 2, 3 and 7.
7 S passive Source of the MOSFET; must be tied common with pins 2, 3 and 6.
8 D passive Drain of the P-channel MOSFET, connected together with pins 1 and 5.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TSSOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS -12 V 1
Gate-Source Voltage VGS -8 8 V 1
Continuous Drain Current, 10 s ID -9.5 A TJ = 150 °C, TA = 25 °C, 10 s 1
Continuous Drain Current, steady state ID -8.2 A TJ = 150 °C, TA = 25 °C, steady state 1
Continuous Drain Current, 10 s ID -8 A TA = 70 °C, 10 s 1
Continuous Drain Current, steady state ID -6.5 A TA = 70 °C, steady state 1
Pulsed Drain Current IDM -30 A 10 µs pulse width 1
Continuous Source Current (Diode Conduction), 10 s IS -1.35 A 10 s 1
Continuous Source Current (Diode Conduction), steady state IS -0.95 A steady state 1
Maximum Power Dissipation, 10 s PD 1.5 W TA = 25 °C, 10 s 1
Maximum Power Dissipation, steady state PD 1.05 W TA = 25 °C, steady state 1
Maximum Power Dissipation, 10 s PD 1 W TA = 70 °C, 10 s 1
Maximum Power Dissipation, steady state PD 0.67 W TA = 70 °C, steady state 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Maximum Junction-to-Ambient, t ≤ 10 s RthJA 60 83 °C/W t ≤ 10 s 1
Maximum Junction-to-Ambient, steady state RthJA 100 120 °C/W steady state 1
Maximum Junction-to-Foot, steady state RthJF 35 45 °C/W steady state 1
Gate Threshold Voltage VGS(th) -0.4 -0.8 V VDS = VGS, ID = -400 µA 2
Gate-Body Leakage IGSS -100 100 nA VDS = 0 V, VGS = ±8 V 2
Zero Gate Voltage Drain Current IDSS -1 µA VDS = -12 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS -10 µA VDS = -12 V, VGS = 0 V, TJ = 70 °C 2
On-State Drain Current ID(on) -20 A VDS = -5 V, VGS = -4.5 V 2
Drain-Source On-State Resistance RDS(on) 0.0068 0.0085 Ω VGS = -4.5 V, ID = -9.5 A 2
Drain-Source On-State Resistance RDS(on) 0.0085 0.0106 Ω VGS = -2.5 V, ID = -8.5 A 2
Drain-Source On-State Resistance RDS(on) 0.0112 0.014 Ω VGS = -1.8 V, ID = -7.5 A 2
Diode Forward Voltage VSD -0.58 -1.1 V IS = -1.3 A, VGS = 0 V 2
Total Gate Charge Qg 74 110 nC VDS = -6 V, VGS = -5 V, ID = -9.5 A 2
Turn-On Delay Time td(on) 50 75 ns VDD = -6 V, RL = 6 Ω, ID ≅ -1 A, VGEN = -4.5 V, RG = 6 Ω 2
Rise Time tr 75 110 ns VDD = -6 V, RL = 6 Ω, ID ≅ -1 A, VGEN = -4.5 V, RG = 6 Ω 2
Turn-Off Delay Time td(off) 270 400 ns VDD = -6 V, RL = 6 Ω, ID ≅ -1 A, VGEN = -4.5 V, RG = 6 Ω 2
Fall Time tf 200 300 ns VDD = -6 V, RL = 6 Ω, ID ≅ -1 A, VGEN = -4.5 V, RG = 6 Ω 2
Source-Drain Reverse Recovery Time trr 160 250 ns IF = -1.3 A, di/dt = 100 A/µs 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper overlies the drain pins. The copper plane connects the drain pins 9

CAD (KiCad official)

  • Symbol: SI6423DQ-T1-GE3
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: si6423dq-t1-ge3-etched.step / si6423dq-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si6423dq-t1-ge3.step / si6423dq-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (11 pp, sha256 284f59d3aea17496, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF