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SI4554DY-T1-GE3

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Vishay Intertech MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI4554DY-T1-GE3

Vishay Intertech · MOSFETs · SO-8

SI4554DY-T1-GE3 from Vishay Intertech, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of the first MOSFET in this dual N- and P-channel 40 V device; the datasheet gives VGS of ±20 V absolute maximum for both channels.
2 G1 input Gate terminal of the first MOSFET; the datasheet gives VGS of ±20 V absolute maximum for both channels.
3 S2 passive Source terminal of the second MOSFET in this dual N- and P-channel 40 V device; the datasheet gives VGS of ±20 V absolute maximum for both channels.
4 G2 input Gate terminal of the second MOSFET; the datasheet gives VGS of ±20 V absolute maximum for both channels.
5 D2 passive Drain terminal of the second MOSFET; the datasheet gives VDS of 40 V (N-channel) and -40 V (P-channel) and continuous drain current ratings per channel.
6 D2 passive Drain terminal of the second MOSFET (second drain pin, tied to D2); the datasheet gives VDS of 40 V (N-channel) and -40 V (P-channel).
7 D1 passive Drain terminal of the first MOSFET; the datasheet gives VDS of 40 V (N-channel) and -40 V (P-channel) and continuous drain current ratings per channel.
8 D1 passive Drain terminal of the first MOSFET (second drain pin, tied to D1); the datasheet gives VDS of 40 V (N-channel) and -40 V (P-channel).

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage (N-channel) VDS 40 V 1
Drain-source voltage (P-channel) VDS -40 V 1
Gate-source voltage (N-channel) VGS -20 20 V 1
Gate-source voltage (P-channel) VGS -20 20 V 1
Continuous drain current (N-channel) ID 8 A TC = 25 °C, TJ = 150 °C 1
Continuous drain current (P-channel) ID -8 A TC = 25 °C, TJ = 150 °C 1
Continuous drain current (N-channel) ID 6.8 A TC = 70 °C 1
Continuous drain current (P-channel) ID -6.8 A TC = 70 °C 1
Continuous drain current (P-channel) ID -6.6 A TA = 25 °C 1
Continuous drain current (N-channel) ID 5.4 A TA = 70 °C 1
Continuous drain current (P-channel) ID -5.3 A TA = 70 °C 1
Pulsed drain current (N-channel) IDM 40 A 10 µs pulse width 1
Pulsed drain current (P-channel) IDM -40 A 10 µs pulse width 1
Source-drain current diode current (N-channel) IS 2.6 A TC = 25 °C 1
Source-drain current diode current (P-channel) IS -2.6 A TC = 25 °C 1
Source-drain current diode current (N-channel) IS 1.6 A TA = 25 °C 1
Source-drain current diode current (P-channel) IS -1.6 A TA = 25 °C 1
Single pulse avalanche current (N-channel) IAS 10 A L = 0.1 mH 1
Single pulse avalanche current (P-channel) IAS 20 A L = 0.1 mH 1
Single pulse avalanche energy (N-channel) EAS 5 mJ L = 0.1 mH 1
Single pulse avalanche energy (P-channel) EAS 20 mJ L = 0.1 mH 1
Maximum power dissipation (N-channel) PD 3.1 W TC = 25 °C 1
Maximum power dissipation (P-channel) PD 3.2 W TC = 25 °C 1
Maximum power dissipation (N-channel) PD 2 W TC = 70 °C 1
Maximum power dissipation (P-channel) PD 2.1 W TC = 70 °C 1
Maximum power dissipation (P-channel) PD 2 W TA = 25 °C 1
Maximum power dissipation (N-channel) PD 1.28 W TA = 70 °C 1
Maximum power dissipation (P-channel) PD 1.28 W TA = 70 °C 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Maximum junction-to-ambient (N-channel) RthJA 50 62.5 °C/W t ≤ 10 s 1
Maximum junction-to-ambient (P-channel) RthJA 47 62.5 °C/W t ≤ 10 s 1
Maximum junction-to-foot (drain) (N-channel) RthJF 30 40 °C/W Steady state 1
Maximum junction-to-foot (drain) (P-channel) RthJF 29 38 °C/W Steady state 1
Drain-source breakdown voltage (N-channel) VDS 40 V VGS = 0 V, ID = 250 µA 2
Drain-source breakdown voltage (P-channel) VDS -40 V VGS = 0 V, ID = -250 µA 2
Gate threshold voltage (N-channel) VGS(th) 1 2.2 V VDS = VGS, ID = 250 µA 2
Gate threshold voltage (P-channel) VGS(th) -1.2 -2.5 V VDS = VGS, ID = -250 µA 2
Gate-body leakage (N-channel) IGSS -100 100 nA VDS = 0 V, VGS = ±20 V 2
Gate-body leakage (P-channel) IGSS -100 100 nA VDS = 0 V, VGS = ±20 V 2
Zero gate voltage drain current (N-channel) IDSS 1 µA VDS = 40 V, VGS = 0 V 2
Zero gate voltage drain current (P-channel) IDSS -1 µA VDS = -40 V, VGS = 0 V 2
On-state drain current (N-channel) ID(on) 20 A VDS = 5 V, VGS = 10 V 2
On-state drain current (P-channel) ID(on) -20 A VDS = -5 V, VGS = -10 V 2
Drain-source on-state resistance (N-channel) RDS(on) 0.02 0.024 Ω VGS = 10 V, ID = 6.8 A 2
Drain-source on-state resistance (P-channel) RDS(on) 0.021 0.027 Ω VGS = -10 V, ID = -8 A 2
Drain-source on-state resistance (N-channel) RDS(on) 0.021 0.026 Ω VGS = 8 V, ID = 6.7 A 2
Drain-source on-state resistance (P-channel) RDS(on) 0.022 0.028 Ω VGS = -8 V, ID = -6.5 A 2
Drain-source on-state resistance (N-channel) RDS(on) 0.022 0.027 Ω VGS = 4.5 V, ID = 6.6 A 2
Drain-source on-state resistance (P-channel) RDS(on) 0.027 0.034 Ω VGS = -4.5 V, ID = -5 A 2
Total gate charge (N-channel) Qg 13.3 20 nC VDS = 20 V, VGS = 10 V, ID = 10 A 2
Total gate charge (P-channel) Qg 41.5 63 nC VDS = -20 V, VGS = -10 V, ID = -10 A 2
Total gate charge at 4.5 V (N-channel) Qg 6.5 10 nC VDS = 20 V, VGS = 4.5 V, ID = 10 A 2
Total gate charge at 4.5 V (P-channel) Qg 21.7 33 nC VDS = -20 V, VGS = -4.5 V, ID = -10 A 2
Gate resistance (N-channel) Rg 0.3 1.3 2.6 Ω f = 1 MHz 2
Gate resistance (P-channel) Rg 1.3 6.4 12.8 Ω f = 1 MHz 2
Body diode voltage (N-channel) VSD 0.81 1.2 V IS = 5.4 A 3
Body diode voltage (P-channel) VSD -0.77 -1.2 V IS = -2 A 3

CAD (KiCad official)

  • Symbol: SI4554DY-T1-GE3
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: si4554dy-t1-ge3-etched.step / si4554dy-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si4554dy-t1-ge3.step / si4554dy-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (14 pp, sha256 58cd0ede93ba4fe3, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF