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SI3440DV-T1-E3

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Vishay Intertech MOSFETs, TSOP-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI3440DV-T1-E3

Vishay Intertech · MOSFETs · TSOP-6

SI3440DV-T1-E3 from Vishay Intertech, in a TSOP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D passive Drain terminal; pins 1, 2, 5 and 6 are connected together as the drain, rated for VDS = 150 V.
2 D passive Drain terminal; pins 1, 2, 5 and 6 are connected together as the drain, rated for VDS = 150 V.
3 G input Gate terminal; gate-source voltage is rated at ±20 V.
4 S passive Source terminal; continuous source (diode conduction) current is rated at 1.7 A for 5 s and 1.0 A steady state at TA = 25 °C.
5 D passive Drain terminal; pins 1, 2, 5 and 6 are connected together as the drain, rated for VDS = 150 V.
6 D passive Drain terminal; pins 1, 2, 5 and 6 are connected together as the drain, rated for VDS = 150 V.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package TSOP-6
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate Threshold Voltage VGS(th) 2 4 V VDS = VGS, ID = 250 µA 2
Gate-Body Leakage IGSS -100 100 nA VDS = 0 V, VGS = ± 20 V 2
Zero Gate Voltage Drain Current IDSS 1 µA VDS = 150 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS 5 µA VDS = 150 V, VGS = 0 V, TJ = 85 °C 2
On-State Drain Current ID(on) 4 A VDS ≥ 5 V, VGS = 10 V 2
Drain-Source On-State Resistance RDS(on) 0.31 0.375 Ω VGS = 10 V, ID = 1.5 A 2
Drain-Source On-State Resistance RDS(on) 0.33 0.4 Ω VGS = 6.0 V, ID = 1.4 A 2
Diode Forward Voltage VSD 0.8 1.2 V IS = 1.7 A, VGS = 0 V 2
Total Gate Charge Qg 5.4 8 nC VDS = 75 V, VGS = 10 V, ID = 1.5 A 2
Gate Resistance Rg 4 9 15 Ω f = 1 MHz 2
Turn-On Delay Time td(on) 8 15 ns VDD = 75 V, RL = 75 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Rise Time tr 10 15 ns VDD = 75 V, RL = 75 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Turn-Off Delay Time td(off) 20 30 ns VDD = 75 V, RL = 75 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Fall Time tf 15 25 ns VDD = 75 V, RL = 75 Ω, ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 2
Source-Drain Reverse Recovery Time trr 40 60 ns IF = 1.7 A, dI/dt = 100 A/µs 2
Drain-Source Voltage VDS 150 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current (TJ = 175 °C), TA = 25 °C, 5 s ID 1.5 A TJ = 175 °C, TA = 25 °C, t ≤ 5 s 1
Continuous Drain Current (TJ = 175 °C), TA = 25 °C, steady state ID 1.2 A TJ = 175 °C, TA = 25 °C, steady state 1
Continuous Drain Current (TJ = 175 °C), TA = 85 °C, 5 s ID 1.1 A TJ = 175 °C, TA = 85 °C, t ≤ 5 s 1
Continuous Drain Current (TJ = 175 °C), TA = 85 °C, steady state ID 0.8 A TJ = 175 °C, TA = 85 °C, steady state 1
Pulsed Drain Current IDM 6 A 1
Single Avalanche Current IAS 4 A L = 0.1 mH 1
Single Avalanche Energy EAS 0.8 mJ L = 0.1 mH, duty cycle ≤ 1 % 1
Continuous Source Current (Diode Conduction), 5 s IS 1.7 A t ≤ 5 s 1
Continuous Source Current (Diode Conduction), steady state IS 1 A Steady State 1
Maximum Power Dissipation, TA = 25 °C, 5 s PD 2 W TA = 25 °C, t ≤ 5 s 1
Maximum Power Dissipation, TA = 25 °C, steady state PD 1.14 W TA = 25 °C, Steady State 1
Maximum Power Dissipation, TA = 85 °C, 5 s PD 1 W TA = 85 °C, t ≤ 5 s 1
Maximum Power Dissipation, TA = 85 °C, steady state PD 0.59 W TA = 85 °C, Steady State 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Maximum Junction-to-Ambient RthJA 45 62.5 °C/W t ≤ 5 s 1
Maximum Junction-to-Ambient RthJA 90 110 °C/W Steady State 1
Maximum Junction-to-Foot (Drain) RthJF 25 30 °C/W Steady State 1

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper pins 1,2,5, and 6. The copper plane connects the drain pins 7

CAD (KiCad official)

  • Symbol: SI3440DV-T1-E3
  • Footprint: Package_SO:TSOP-6_1.65x3.05mm_P0.95mm
  • 3D model: TSOP-6 (KiCad packages3D, STEP)
  • 3D model files: si3440dv-t1-e3-etched.step / si3440dv-t1-e3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si3440dv-t1-e3.step / si3440dv-t1-e3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (10 pp, sha256 05e30ceaff339682, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF