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SI2319DDS-T1-GE3

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Vishay Intertech MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SI2319DDS-T1-GE3

Vishay Intertech · MOSFETs · SOT-23

SI2319DDS-T1-GE3 from Vishay Intertech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G input Gate of the P-channel MOSFET, rated for gate-source voltage VGS of ±20 V.
2 S passive Source of the P-channel MOSFET, with continuous source-drain diode current IS of -1.4 A at TC = 25 °C.
3 D passive Drain of the P-channel MOSFET, rated for drain-source voltage VDS of -40 V and continuous drain current ID of -3.6 A at TC = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDS -40 V 1
Gate-source voltage VGS -20 20 V 1
Continuous drain current ID -3.6 A TJ = 150 °C, TC = 25 °C 1
Continuous drain current ID -2.9 A TJ = 150 °C, TC = 70 °C 1
Continuous drain current ID -2.7 A TJ = 150 °C, TA = 25 °C, notes b, c 1
Continuous drain current ID -2.2 A TJ = 150 °C, TA = 70 °C, notes b, c 1
Pulsed drain current IDM -15 A t = 100 μs 1
Continuous source-drain diode current IS -1.4 A TC = 25 °C 1
Continuous source-drain diode current IS -0.8 A TA = 25 °C, notes b, c 1
Single pulse avalanche current IAS -5 A L = 0.1 mH 1
Single pulse avalanche energy EAS 1.25 mJ 1
Maximum power dissipation IP 1.7 W TC = 25 °C 1
Maximum power dissipation IP 1.1 W TC = 70 °C 1
Maximum power dissipation IP 1 W TA = 25 °C, notes b, c 1
Maximum power dissipation IP 0.6 W TA = 70 °C, notes b, c 1
Operating junction and storage temperature range TJ, Tstg -55 150 °C 1
Maximum junction-to-ambient RthJA 100 130 °C/W t ≤ 5 s, note b 1
Maximum junction-to-case (drain) RthJF 60 75 °C/W Steady state 1
Maximum junction-to-ambient (steady state) RthJA 175 °C/W Steady state, note d 1
Drain-source breakdown voltage VDS -40 V VGS = 0 V, ID = -250 μA 2
Gate-source threshold voltage VGS(th) -1 -2.5 V VDS = VGS, ID = 250 μA 2
Gate-source leakage IGSS 100 nA VDS = 0 V, VGS = ±20 V 2
Zero gate voltage drain current IDSS -1 μA VDS = -40 V, VGS = 0 V 2
Zero gate voltage drain current IDSS -15 μA VDS = -40 V, VGS = 0 V, TJ = 70 °C 2
On-state drain current ID(on) -10 A VDS ≤ -10 V, VGS = -10 V 2
Drain-source on-state resistance RDS(on) 0.062 0.075 Ω VGS = -10 V, ID = -2.7 A 2
Drain-source on-state resistance RDS(on) 0.081 0.1 Ω VGS = -4.5 V, ID = -2.4 A 2
Total gate charge Qg 12.5 19 nC VDS = -20 V, VGS = -10 V, ID = -2.7 A 2
Total gate charge Qg 6 12 nC VDS = -20 V, VGS = -4.5 V, ID = -2.7 A 2
Gate resistance Rg 2 10 20 Ω f = 1 MHz 2
Turn-on delay time td(on) 10 20 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -10 V, Rg = 1 Ω 2
Rise time tr 20 30 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-off delay time td(off) 20 30 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -10 V, Rg = 1 Ω 2
Fall time tf 12 24 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -10 V, Rg = 1 Ω 2
Turn-on delay time td(on) 30 45 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -4.5 V, Rg = 1 Ω 2
Rise time tr 32 48 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -4.5 V, Rg = 1 Ω 2
Fall time tf 15 30 ns VDD = -20 V, RL = 9.1 Ω, ID ≤ -2.2 A, VGEN = -4.5 V, Rg = 1 Ω 2
Continuous source-drain diode current IS -1.4 A TC = 25 °C 2
Pulse diode forward current ISM -15 A 2
Body diode voltage VSD -0.8 -1.2 V IS = -2.2 A, VGS = 0 V 2
Body diode reverse recovery time trr 15 30 ns IF = -2.2 A, di/dt = 100 A/μs, TJ = 25 °C 2
Body diode reverse recovery charge Qrr 9 18 nC 2

CAD (KiCad official)

  • Symbol: SI2319DDS-T1-GE3
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: si2319dds-t1-ge3-etched.step / si2319dds-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si2319dds-t1-ge3.step / si2319dds-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (9 pp, sha256 50f2a01bd9b241e5, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF