main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers si1024x-t1-ge3: viewers · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3-etched.glb Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3-etched.step si1024x-t1-ge3: factory component page (tier=lcsc) · Ray 17d ago
si1024x-t1-ge3-hero.glb si1024x-t1-ge3: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
si1024x-t1-ge3-hero.overlay.json Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3.glb Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3.kicad_mod Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3.kicad_sym Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3.lbr Publish 0.1.0 · Ray 17d ago
si1024x-t1-ge3.step Publish 0.1.0 · Ray 17d ago

SI1024X-T1-GE3

Vishay Intertech · MOSFETs · SOT-563

SI1024X-T1-GE3 from Vishay Intertech, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of MOSFET 1; the datasheet shows a 100 Ω gate resistor and ESD protection on the gate of each MOSFET (gate-source ESD rated 2000 V HBM).
2 G1 input Gate of MOSFET 1, ESD protected with an internal 100 Ω series resistor, absolute maximum gate-source voltage ±6 V and threshold 0.45 to 0.9 V.
3 D2 passive Drain of MOSFET 2, rated 20 V drain-source maximum with 485 mA continuous drain current at steady state, TA = 25 °C.
4 S2 passive Source of MOSFET 2, with continuous source (diode) current of 380 mA steady state.
5 G2 input Gate of MOSFET 2, ESD protected with an internal 100 Ω series resistor, absolute maximum gate-source voltage ±6 V and threshold 0.45 to 0.9 V.
6 D1 passive Drain of MOSFET 1, rated 20 V drain-source maximum with 485 mA continuous drain current at steady state, TA = 25 °C.

Key specifications

Parameter Value
Manufacturer Vishay Intertech
Package SOT-563
Category Transistors/Thyristors
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage VDS 20 V 1
Gate-Source Voltage VGS -6 6 V 1
Continuous Drain Current ID 515 mA TJ = 150 °C, TA = 25 °C, 5 s 1
Continuous Drain Current ID 485 mA TJ = 150 °C, TA = 25 °C, steady state 1
Continuous Drain Current ID 370 mA TJ = 150 °C, TA = 85 °C, 5 s 1
Continuous Drain Current ID 350 mA TJ = 150 °C, TA = 85 °C, steady state 1
Pulsed Drain Current IDM 650 mA Pulse width limited by maximum junction temperature (note b) 1
Continuous Source Current (Diode Conduction) IS 450 mA TA = 25 °C, 5 s 1
Continuous Source Current (Diode Conduction) IS 380 mA TA = 25 °C, steady state 1
Maximum Power Dissipation PD 280 mW TA = 25 °C, 5 s 1
Maximum Power Dissipation PD 250 mW TA = 25 °C, steady state 1
Maximum Power Dissipation PD 145 mW TA = 85 °C, 5 s 1
Maximum Power Dissipation PD 130 mW TA = 85 °C, steady state 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Gate-Source ESD Rating (HBM) ESD 2000 V HBM, Method 3015 1
Gate Threshold Voltage VGS(th) 0.45 0.9 V VDS = VGS, ID = 250 µA 2
Gate-Body Leakage IGSS -1 1 µA VDS = 0 V, VGS = ± 4.5 V 2
Zero Gate Voltage Drain Current IDSS 0.3 100 nA VDS = 20 V, VGS = 0 V 2
Zero Gate Voltage Drain Current IDSS 5 µA VDS = 20 V, VGS = 0 V, TJ = 85 °C 2
Drain-Source On-State Resistance RDS(on) 0.41 0.7 Ω VGS = 4.5 V, ID = 600 mA 2
Drain-Source On-State Resistance RDS(on) 0.53 0.85 Ω VGS = 2.5 V, ID = 500 mA 2
Drain-Source On-State Resistance RDS(on) 0.7 1.25 Ω VGS = 1.8 V, ID = 350 mA 2
Diode Forward Voltage VSD 0.8 1.2 V IS = 150 mA, VGS = 0 V 2
Thermal Resistance, Junction-to-Ambient RthJA 500 °C/W Per unit base, surface mounted (page 4 figure note 2) 4

CAD (KiCad official)

  • Symbol: SI1024X-T1-GE3
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: si1024x-t1-ge3-etched.step / si1024x-t1-ge3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); si1024x-t1-ge3.step / si1024x-t1-ge3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Vishay Intertech datasheet (7 pp, sha256 ce7a2ed23aba35a6, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF