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SD2057

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Hangzhou SDIC Microelectronics Interface - Specialized, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SD2057

Hangzhou SDIC Microelectronics · Interface - Specialized · QFN-24-EP(4x4)

SD2057 from Hangzhou SDIC Microelectronics, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTAL_ENb input Active-low crystal oscillator enable that, together with CLK_CFG0/CLK_CFG1, selects the clock configuration per Table 2.
2 CLKOUT output Clock output at the DVDD logic level, selectable per Table 2; driving its load adds supply current (I = C×V×f), so the load should be kept small.
3 CLK_CFG0 input Clock configuration control input that selects the system clock and CLKOUT mode per Table 2.
4 CLK_CFG1 input Clock configuration control input that selects the system clock and CLKOUT mode per Table 2.
5 RESETb input Active-low chip reset; when low the device enters power-save mode with maximum 5 µA consumption, and it may be tied to DVDD if reset is not used.
6 CD output Carrier detect output that is high when a valid carrier is present on HART_IN.
7 TXD input Transmit data NRZ input to the modulator, whose modulated output is sent on HART_OUT.
8 RTSb input Active-low request-to-send that enables the modulator and disables the demodulator (transmit mode); high enables the demodulator and disables the modulator (receive mode).
9 DUPLEX input Active-high full-duplex enable; with RTSb low it enables simultaneous modulator and demodulator operation for loopback self-test.
10 RXD output Demodulated HART data output sent to the external UART.
11 DVDD power_in Digital supply, which must be the same voltage as AVDD (2.7 to 5.5 V); decouple with parallel 1 µF and 0.1 µF low-ESR capacitors.
12 DVSS power_in Digital ground that must be connected to AVSS.
13 REG_CAP output Output of the internal LDO (about 2 V) supplying the digital core; decouple with a 1 µF ceramic capacitor to DVSS.
14 HART_OUT output HART FSK output to the 4-20 mA loop with 0.75 V DC level and 0.5-1.0 V swing; use 4.7 nF to 68 nF capacitive load, and maximum resistive load is 160 Ω.
15 REF bidirectional Internal 1.5 V reference output, or external 2.5 V reference input when REF_EN is low; decouple with 1 µF to AVSS.
16 HART_IN input HART FSK input from the 4-20 mA loop with an input range of 0 to 1.5 V when the internal reference is used.
17 ADC_IP input ADC input fed from an external bandpass filter output; when the internal filter is used, connect a 680 pF capacitor to AVSS.
18 AVDD power_in Analog supply (2.7 to 5.5 V) that must match DVDD; decouple with parallel 1 µF and 0.1 µF low-ESR capacitors.
19 AVSS power_in Analog ground.
20 XTAL2 output Crystal connection for the external 3.6864 MHz crystal; leave open when an external CMOS clock is applied to XTAL1.
21 XTAL1 input Crystal connection for the 3.6864 MHz oscillator or external CMOS clock input.
22 DVSS power_in Digital ground that must be connected to AVSS.
23 REF_EN input Reference enable; high enables the internal 1.5 V reference and buffer, low disables them and requires an external 2.5 V buffered reference on REF.
24 FILTER_SEL input Bandpass filter select; high enables the internal filter with HART signal on HART_IN, low disables it and requires an external filter output on ADC_IP.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Hangzhou SDIC Microelectronics
Package QFN-24-EP(4x4)
Category Interface
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
工作温度 TA TA -55 125 ℃ 8
储存温度 TS TS -65 150 ℃ 8
模拟供电电压 AVDD 至 AVSS AVDD -0.3 7 V 8
数字供电电压 DVDD 至 DVSS DVDD -0.3 7 V 8
模拟数字电源地 AVSS 至 DVSS -0.3 0.3 V 8
模拟端口偏压 模拟输入至 AVSS -0.3 V 最大值印刷为 AVDD+0.3 或+7(取较小者) 8
数字端口偏压 数字输入至 DVSS -0.3 V 最大值印刷为 DVDD+0.3 或+7(取较小者) 8
封装热阻 θJA θJA 50 ℃/W 8
ESD 人体模型 4000 V 8
ESD 机械模型 400 V 8
电源电压 AVDD/DVDD 2.7 3.3 5.5 V 8
功耗解调模式 IDD1 IDD1 113 148 µA 外部时钟、-55℃至+85℃ 8
功耗解调模式 IDD1 IDD1 168 µA 外部时钟、-55℃至+125℃ 8
功耗解调模式 IDD1 (外部基准) IDD1 93 120 µA 外部时钟、-55℃至+85℃、外部基准电压源 8
功耗解调模式 IDD1 (外部基准) IDD1 141 µA 外部时钟、-55℃至+125℃、外部基准电压源 8
功耗调制模式 IDD1 IDD1 76 97 µA 外部时钟、-55℃至+85℃ 8
功耗调制模式 IDD1 IDD1 112 µA 外部时钟、-55℃至+125℃ 8
功耗调制模式 IDD1 (外部基准) IDD1 56 77 µA 外部时钟、-55℃至+85℃、外部基准电压源 8
功耗调制模式 IDD1 (外部基准) IDD1 92 µA 外部时钟、-55℃至+125℃、外部基准电压源 8
省电模式功耗 IDD0 2.5 5 µA 8
晶振功耗 IOSC 45 90 µA 外部晶振、XTAL1/2 各接 8pF 负载 8
内部 VREF 初始精度 1.48 1.5 1.52 V REF_EN = DVDD 8
外部 VREF 初始精度 2.47 2.5 2.53 V REF_EN = DVSS 8
外部 VREF 输入电流 解调模式 IREF 3.4 5 µA 解调模式 8
外部 VREF 输入电流 调制模式 IREF 2.7 4 µA 调制模式 8
载波有效幅度 90 105 115 mVp-p 9
HART_IN 输入范围 (外部基准) 0 V 使用外部基准电压条件下，最大值印刷为 REF 9
HART_IN 输入范围 (内部基准) 0 1.5 V 使用内部基准电压条件下 9
HART_OUT 输出幅度 465 500 518 mVp-p HART_OUT，负载如图 4 所示 9
相位连续性误差 0 度 9
数字输入高电平电流 IIH IIH -0.1 0.1 µA 9
数字输入低电平电流 IIL IIL -0.1 0.1 µA 9
外部时钟频率精度 (3.6864MHz) 3.6496 3.6864 3.7232 MHz 外灌 3.6864MHz 条件下 9
外部时钟频率精度 (1.2288MHz) 1.2165 1.2288 1.2411 MHz 外灌 1.2288MHz 条件下 9
载波起始时间 t1 t1 0.3 位时间 从 RTSb 下降沿到载波到达第一个波峰 9
载波停止时间 t2 t2 1 位时间 从 RTSb 上升沿到载波幅度降至最小接收幅度以下 9
载波衰减时间 t3 t3 1 位时间 从 RTSb 上升沿到载波幅度降至交流零 9
载波检测开启 t4 t4 6 位时间 从载波开启到 CD 上升沿 9
载波检测关闭 t5 t5 6 位时间 从载波关闭到 CD 下降沿 9
逻辑“1”频率 1200 Hz 9
逻辑“0”频率 2200 Hz 9
最大阻性负载 160 Ω 负载如图 4 所示的 RLOAD 9
发送阻抗 17 Ω RTSb 低电平、HART_OUT 引脚处 9
负载调整率 1.5 ppm/µA 利用 500µA 负载测试 8
电压调整率 60 µV/V 8
晶振上电时间 t6 t6 24.5 ms XTAL1/2 各接 8pF 对地负载电容 9
REF 上电时间 t7 t7 0.5 ms 内部基准电压源 9
唤醒时间 t8 t8 18 µs 从省电模式到正常工作模式的转换时间（外灌时钟、外部基准电压源） 9

CAD (KiCad official)

  • Symbol: SD2057
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: sd2057-etched.step / sd2057-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sd2057.step / sd2057.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Hangzhou SDIC Microelectronics datasheet (12 pp, sha256 3d7981dffd44edac, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF