component

SCT9320STDR

Public Made by Adom

by adom

SCT DC-DC Converters, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sct9320stdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sct9320stdr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md sct9320stdr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sct9320stdr-etched.fit.json sct9320stdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct9320stdr-etched.glb sct9320stdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct9320stdr-etched.step sct9320stdr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct9320stdr.glb Publish 0.1.0 · Ray
sct9320stdr.kicad_mod Publish 0.1.0 · Ray
sct9320stdr.kicad_sym Publish 0.1.0 · Ray
sct9320stdr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sct9320stdr.step Publish 0.1.0 · Ray

SCT9320STDR

SCT · DC-DC Converters · SOIC-8

SCT9320STDR from SCT, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Bootstrap supply for the high-side MOSFET gate driver. Connect a 0.1 µF (or greater) ceramic capacitor between BOOT and SW; the cap is refreshed when the low-side FET turns on.
2 VIN power_in Power supply input, 3.8 V to 32 V. Must be locally bypassed with a low-ESR ceramic capacitor placed close to the pin.
3 EN input Enable logic input. Floating the pin enables the device; can be tied directly to VIN (rated up to 34 V). Precision enable thresholds: 1.18 V rising / 1.1 V falling for programmable UVLO with hysteresis.
4 NC unconnected Not connected. Leave floating or tie to a copper island for thermal relief; no internal connection.
5 FB input Buck converter output feedback sensing input. Connect a resistor divider from VOUT to FB to set the output voltage; the internal reference regulates FB to 0.8 V typical (0.792 V-0.808 V).
6 NC unconnected Not connected. Leave floating or tie to a copper island for thermal relief; no internal connection.
7 GND power_in Power ground return for the low-side MOSFET and controller. Must be soldered directly to the ground plane with a low-impedance connection.
8 SW power_out Switching node of the buck converter. Connect to the output inductor and to the BOOT capacitor. High dV/dt node; keep trace short and shielded to minimize EMI.

Key specifications

Parameter Value
Manufacturer SCT
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SCT9320STDR

CAD (KiCad official)

  • Symbol: SCT9320STDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: sct9320stdr-etched.step / sct9320stdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sct9320stdr.step / sct9320stdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SCT datasheet (20 pp, sha256 3cd46ac0287aaae0, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF