component

SCT2630STER

Public Made by Adom

by adom

SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs sct2630ster: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sct2630ster: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
README.md sct2630ster: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
sct2630ster-etched.fit.json sct2630ster: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct2630ster-etched.glb sct2630ster: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct2630ster-etched.step sct2630ster: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sct2630ster.glb fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body… · Ray
sct2630ster.kicad_mod Publish 0.1.0 · Ray
sct2630ster.kicad_sym Publish 0.1.0 · Ray
sct2630ster.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sct2630ster.step fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm (3d refresh; body… · Ray

SCT2630STER

SCT · DC-DC Converters · ESOP-8

SCT2630STER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Bootstrap supply for the high-side power MOSFET gate driver. Connect a 0.1uF capacitor from BOOT to SW; the cap is charged when SW is low. Absolute max 72V; BOOT-SW absolute max 6V.
2 VIN power_in Input supply voltage, 4.2V to 60V operating (absolute max 65V). Connect a local high-frequency bypass capacitor from VIN to GND with the shortest possible path.
3 EN input Enable pin with internal 1uA/4uA pull-up current source. Pull below 1.05V to disable, above 1.2V to enable. May float or tie to VIN to auto-enable; a VIN-to-GND resistor divider on EN sets a programmable UVLO threshold. Absolute max 65V.
4 RT/CLK bidirectional Sets internal oscillator frequency via a resistor to GND (100 kHz-1.2 MHz), or accepts an external clock for PLL sync (100 kHz-1.2 MHz, high ≥2V, low ≤0.4V, pulse width >80ns). Typical pin voltage 0.5V in RT mode. If external clock stops, mode reverts automatically to resistor-programmed frequency. Absolute max 6V.
5 FB input Inverting input of the trans-conductance error amplifier. External resistor divider from VOUT to GND ties to FB; device regulates FB to the internal 0.8V (±1%) reference. Absolute max 6V.
6 COMP output Error amplifier output for external loop compensation network (typ. series R-C to GND). COMP clamps at ~2.25V high and ~0.47V low; EA gm = 240 µA/V, source/sink current 24 µA. Absolute max 6V.
7 GND power_in Device ground return. Connect directly to the input bypass capacitor return with a low-impedance path; tie to the exposed thermal pad.
8 SW power_out Switching node - source of the internal 220mΩ high-side MOSFET. Connect to the external power inductor and (for asynchronous operation) the anode of a Schottky freewheeling diode. Absolute max range -1V to 65V.
9 Thermal Pad power_in Exposed die-pad for heat dissipation. Electrically connected to GND (pin 7) and must be soldered to the PCB ground plane for proper operation and optimum thermal performance (θJA ≈ 42 °C/W).

Key specifications

Parameter Value
Manufacturer SCT
Package ESOP-8
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • SCT2630STER

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage on VIN and EN pins VIN, EN -0.3 65 V 2
BOOT pin voltage BOOT -0.3 72 V 2
SW pin voltage SW -1 65 V 2
BOOT-SW voltage BOOT-SW -0.3 6 V 2
COMP, FB, RT/CLK voltage COMP, FB, RT/CLK -0.3 6 V 2
Operating junction temperature TJ -40 150 °C 2
Storage temperature TSTG -65 150 °C 2
Input voltage range VIN 4.5 60 V 3
Output voltage range VOUT 0.8 57 V 3
Operating junction temperature TJ -40 150 °C 3
Operating input voltage VIN 4.2 60 V 3
Reference voltage of FB VREF 0.792 0.8 0.808 V 3
High-side MOSFET peak current limit threshold ILIM_HS 4.6 5.2 5.8 A 4
Frequency range using RT mode FRANGE_RT 100 1200 kHz 4
Switching frequency FSW 450 500 550 kHz RRT=200 kΩ(1%) 4
Frequency range using CLK mode FRANGE_CLK 100 1200 kHz 4
Input UVLO threshold, VIN rising VIN_UVLO 3.5 V VIN rising 3
Input UVLO hysteresis 400 mV 3
Shutdown current from VIN pin ISHDN 2 5 μA EN=0, no load 3
Quiescent current from VIN pin IQ 190 μA EN floating, no load, non-switching, BOOT-SW=5V, RRT=200 kΩ 3
High-side MOSFET on-resistance RDSON_H 220 mΩ VBOOT-VSW=5V 3
Error amplifier trans-conductance GEA 240 μA/V -2μA<ICOMP<2μA, VCOMP=1V 3
EA maximum source current ICOMP_SRC 24 μA VFB=VREF-100mV, VCOMP=1V 3
EA maximum sink current ICOMP_SNK 24 μA VFB=VREF+100mV, VCOMP=1V 3
COMP high clamp VCOMP_H 2.25 V 3
COMP low clamp VCOMP_L 0.47 V 4
Over current protection hiccup wait time THIC_W 512 cycles 4
Over current protection hiccup restart time THIC_R 8192 cycles 4
Enable high threshold VEN_H 1.2 V 4
Enable low threshold VEN_L 1.05 V 4
Enable pin pull-up current IEN_L 1 μA EN=1V 4
Enable pin pull-up current IEN_H 4 μA EN=1.5V 4
Soft start time TSS 4 ms 4
Minimum on-time tON_MIN 100 ns VIN=24V 4
Feedback overvoltage, VFB/VREF rising VOVP 110 % 4
Feedback overvoltage, VFB/VREF falling VOVP 105 % 4
BOOT UVLO reference voltage VBOOTUV 2.5 V BOOT-SW falling 4
BOOT UVLO hysteresis 230 mV 4
Thermal shutdown threshold TSD 172 °C TJ rising 4
Thermal shutdown hysteresis 12 °C 4
Junction-to-ambient thermal resistance (standard board) θJA 42 °C/W standard board 3
Junction-to-top characterization parameter ψJT 5.9 °C/W 3

CAD (KiCad official)

  • Symbol: SCT2630STER
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: sct2630ster-etched.step / sct2630ster-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sct2630ster.step / sct2630ster.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sct2630ster.step 193 KB You want the bare part, or you mark your own boards.
sct2630ster-etched.step 2.3 MB You want the part with SCT2630STER already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 550 faces against 63 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SCT datasheet (22 pp, sha256 9efec8f7038ae171, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF