component
SCT2620MRER
Public Made by Adomby adom
SCT DC-DC Converters, MSOP-10-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
Contents
README
markdownSCT2620MRER
SCT · DC-DC Converters · MSOP-10-EP
SCT2620MRER from SCT, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Power supply bias for high-side power MOSFET gate driver. Connect a 0.1 µF bootstrap capacitor from BOOT to SW; charged when SW voltage is low. Abs max 72 V. BOOT-SW UVLO ~2.5 V. |
| 2 | VIN | power_in | Input supply voltage, 3.8 V to 60 V (abs max 65 V). Connect a local bypass capacitor from VIN to GND with the shortest possible path to the high-frequency bypass cap. |
| 3 | EN | input | Enable pin with internal pull-up current (~4 µA at 1.5 V). Pull below 1.05 V to disable the converter; float or tie to VIN to enable. A resistor divider from VIN to GND on EN sets the programmable input UVLO threshold (VEN_H ~1.2 V). |
| 4 | SS/TR | passive | Soft-start and tracking pin. An external capacitor sets the output voltage rise time via a 2.6 µA charge current. The voltage on this pin overrides the internal 0.8 V reference, enabling tracking/sequencing. |
| 5 | RT/CLK | bidirectional | Sets the internal oscillator frequency (100 kHz to 1.2 MHz) via a resistor to GND, or accepts an external clock for PLL synchronization (100 kHz to 1.2 MHz). Reverts to resistor-programmed frequency if the external clock stops. |
| 6 | PWRGD | output | Open-drain power-good output. Asserts low on thermal shutdown, dropout, over-voltage, or EN shutdown. VPG_LOW ≤ 0.1 V at 1 mA sink; leakage ≤ 200 nA at 5 V pull-up. Trips at ~90%/110% of VFB. |
| 7 | FB | input | Inverting input of the trans-conductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND; regulated to VREF = 0.8 V (typ, ±1%). |
| 8 | COMP | output | Error amplifier output. Connect an external frequency loop compensation network (typ R-C to GND). Trans-conductance Gm = 240 µA/V; clamps at 0.47 V (low) / 2.25 V (high). |
| 9 | GND | power_in | Device ground. Should be tied to the thermal pad and to the PCB ground plane for proper operation. |
| 10 | SW | power_out | Regulator switching node - drain of the internal high-side MOSFET (RDSON = 220 mΩ typ). Connect to the external power inductor. Abs max -1 V to 65 V (-5 V for 10 ns transient). Peak current limit ~4.2 A. |
| 11 | PAD | power_in | Exposed thermal pad, heat dissipation path of the die. Electrically connected to GND (pin 9). Must be soldered to the PCB ground plane for proper operation and optimized thermal performance (θJA = 62.5 °C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | MSOP-10-EP |
| Category | PMIC |
| Pins | 11 |
Ordering variants
Same part, different packaging or reel option.
SCT2620MRER
CAD (KiCad official)
- Symbol:
SCT2620MRER - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files:
sct2620mrer-etched.step/sct2620mrer-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sct2620mrer.step/sct2620mrer.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
sct2620mrer.step |
151 KB | You want the bare part, or you mark your own boards. |
sct2620mrer-etched.step |
2.6 MB | You want the part with SCT2620MRER already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 634 faces against 182 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (22 pp, sha256
143e0877463556e0, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).