component
SCT2420STER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSCT2420STER
SCT · DC-DC Converters · ESOP-8
SCT2420STER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Power supply bias for the high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. The capacitor is charged when the low-side MOSFET is on or SW voltage is low. Absolute max rating -0.3V to 46V; BOOT-SW max 6V. |
| 2 | VIN | power_in | Input supply voltage, 3.8V to 40V operating range (absolute max 42V). Connect a local high-frequency bypass capacitor from VIN to GND as close as possible. |
| 3 | EN | input | Enable pin with internal pull-up current source (1.5µA at 1V, 5.5µA at 1.5V). Pull below 1.1V to disable the converter; float or connect to VIN to enable. A resistor divider from VIN to GND on EN sets the input voltage lockout threshold. Enable high threshold typ. 1.18V. |
| 4 | RT/CLK | bidirectional | Sets the internal oscillator clock frequency or synchronizes to an external clock. Connect a resistor from this pin to ground to set switching frequency (100kHz to 2.2MHz; 200kΩ ≈ 500kHz). Alternatively drive with an external clock (100kHz-2.2MHz) for PLL synchronization; automatically reverts to resistor-programmed frequency if clock stops. |
| 5 | FB | input | Inverting input of the trans-conductance error amplifier. External feedback resistor divider from VOUT to GND sets the output voltage; device regulates FB to the internal 0.8V (±1%) reference. |
| 6 | COMP | output | Error amplifier output. Connect to the frequency loop compensation network (typically an R-C to GND). COMP high clamp 3V, low clamp 0.4V; EA transconductance 300µS. |
| 7 | GND | power_in | Device ground return. Tie to system ground plane along with the thermal pad. |
| 8 | SW | output | Regulator switching node. Connect to an external power inductor. Absolute max rating -0.3V to 42V. |
| 9 | Thermal Pad | passive | Exposed thermal pad on package underside - heat dissipation path from the die. Must be electrically connected to the GND pin and soldered to the PCB ground plane for proper operation and optimal thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SCT2420STER
CAD (KiCad official)
- Symbol:
SCT2420STER - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
sct2420ster-etched.step/sct2420ster-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sct2420ster.step/sct2420ster.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (22 pp, sha256
dbaa901660a31b92, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).