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SC4215ASTRT

Public Made by Adom

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SEMTECH Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SC4215ASTRT

SEMTECH · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

SC4215ASTRT from SEMTECH, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Listed as No Connection in the pin description table, so it is not used by the regulator.
2 EN input Enable input: pulling this pin below 0.4V turns the regulator off and reduces quiescent current to a fraction of its operating value, the device is enabled if left open, and it should be connected to VIN if not used.
3 VIN power_in Input voltage must be between (VO + 0.5V) and 6.0V for full-load regulation with a minimum of 1.4V, and a minimum 4.7µF ceramic capacitor should be placed directly at this pin.
4 NC unconnected Listed as No Connection in the pin description table, so it is not used by the regulator.
5 NC unconnected Listed as No Connection in the pin description table, so it is not used by the regulator.
6 VO power_out Power output of the device, and a minimum 10µF capacitor should be placed directly at this pin.
7 FB input Feedback pin: grounding it sets the output to 1.2V internally, connecting it to VO sets 0.5V, and external feedback resistors set the output by resistor ratio.
8 GND power_in Reference ground that must be connected to the exposed die pad at the IC pin.
9 THERMAL PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SEMTECH
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN, EN, VO, FB to GND (absolute maximum) -0.3 7 V 3
Storage Temperature Range -65 150 °C 3
Maximum Junction Temperature 150 °C 3
Peak IR Reflow Temperature 260 °C 10s to 30s 3
ESD Protection Level 2 kV JEDEC JESD22-A114-B 3
VIN (input voltage, recommended operating range) VIN 1.4 6 V Printed as 1.4 < VIN < 6.0 3
Ambient Temperature Range TA -40 105 °C Printed as -40 < TA < +105 3
Junction Temperature Range TJ -40 125 °C Printed as -40 < TJ < +125 3
Maximum Output Current 2 A 3
Quiescent Current (3.3V, no load) IQ 3 mA VIN = 3.3V, IO = 0A 3
Quiescent Current (shutdown) IQ 10 50 μA VIN = 6.0V, VEN = 0V 3
Output Voltage accuracy (fixed voltage) VO -2 2 % VIN = VO + 0.5V, IO = 10mA 3
Output Voltage accuracy (fixed voltage) VO -3 3 % 1.40V ≤ VIN ≤ 6.0V, IO = 10mA 3
Line Regulation REG (LINE) 0.2 0.4 %/V IO = 10mA 3
Load Regulation REG(LOAD) 0.5 1.5 % IO = 10mA to 2A 3
Dropout Voltage VDO 90 400 mV IO = 1A, 1.4V ≤ VIN < 1.6V 4
Dropout Voltage VDO 200 mV IO = 1A, 1.6V ≤ VIN ≤ 6.0V 4
Dropout Voltage VDO 200 500 mV IO = 1.5A, 1.4V ≤ VIN < 1.6V 4
Dropout Voltage VDO 300 mV IO = 1.5A, 1.6V ≤ VIN ≤ 6.0V 4
Dropout Voltage VDO 300 600 mV IO = 2A, 1.4V ≤ VIN < 1.6V 4
Dropout Voltage VDO 400 mV IO = 2A, 1.6V ≤ VIN ≤ 6.0V 4
Minimum Load Current IO 10 μA 4
Current Limit ICL 2.1 3 4.4 A 4
Reference Voltage VREF 0.495 0.5 0.505 V VIN = 3.3V, VFB = VOUT, IO = 10mA 4
Reference Voltage VREF 0.49 0.51 V 4
Feedback Pin Current IADJ 80 200 nA VFB = VREF 4
Feedback Pin Threshold VTH(FB) 0.05 0.1 0.15 V 4
Enable Pin Current IEN 1.5 10 μA VEN = 0V, VIN = 3.3V 4
Enable Pin Threshold (high) VIH 1.6 V VIN = 3.3V 4
Enable Pin Threshold (low) VIL 0.4 V 4
Over Temperature Protection High Trip Level THI 160 °C 4
Over Temperature Protection Hysteresis THYST 10 °C 4
Thermal Resistance, Junction to Ambient 36 °C/W Still air, 3" x 4.5" 4-layer FR4 PCB with thermal vias, per JESD51 3
Thermal Resistance, Junction to Case 5.5 °C/W Still air, 3" x 4.5" 4-layer FR4 PCB with thermal vias, per JESD51 3

CAD (KiCad official)

  • Symbol: SC4215ASTRT
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: sc4215astrt-etched.step / sc4215astrt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sc4215astrt.step / sc4215astrt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SEMTECH datasheet (10 pp, sha256 96d943e6b70672f8, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF