component

S-LMUN5311DW1T1G

Public Made by Adom

by adom

LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs s-lmun5311dw1t1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers s-lmun5311dw1t1g: viewers · Ray 1mo ago
package.json s-lmun5311dw1t1g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json s-lmun5311dw1t1g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/s-lmun5311dw1t1g · Ray 1mo ago
s-lmun5311dw1t1g-etched.fit.json s-lmun5311dw1t1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
s-lmun5311dw1t1g-etched.glb s-lmun5311dw1t1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
s-lmun5311dw1t1g-etched.step s-lmun5311dw1t1g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
s-lmun5311dw1t1g.glb Publish 0.1.0 · Ray 1mo ago
s-lmun5311dw1t1g.kicad_mod Publish 0.1.0 · Ray 1mo ago
s-lmun5311dw1t1g.kicad_sym Publish 0.1.0 · Ray 1mo ago
s-lmun5311dw1t1g.lbr Publish 0.1.0 · Ray 1mo ago
s-lmun5311dw1t1g.step Publish 0.1.0 · Ray 1mo ago

S-LMUN5311DW1T1G

LRC · Digital Transistors · SOT-363

S-LMUN5311DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E2 power_in Emitter of PNP transistor Q2, connected to positive supply voltage for Q2 operation and complementary output.
2 B2 input Base of PNP transistor Q2, input terminal with integrated base bias resistor (10 kΩ for LMUN5311DW1T1G) for Q2 control.
3 C1 output Collector of NPN transistor Q1, output terminal with maximum collector-emitter voltage of 50 Vdc and collector current of 100 mAdc.
4 E1 power_in Emitter of NPN transistor Q1, ground reference terminal providing return current path for Q1.
5 B1 input Base of NPN transistor Q1, input terminal with integrated base bias resistor (10 kΩ for LMUN5311DW1T1G) for Q1 control.
6 C2 output Collector of PNP transistor Q2, output terminal with maximum collector-emitter voltage of 50 Vdc and collector current of 100 mAdc.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-363
Category Transistors/Thyristors
Pins 6

CAD (KiCad official)

  • Symbol: S-LMUN5311DW1T1G
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: s-lmun5311dw1t1g-etched.step / s-lmun5311dw1t1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s-lmun5311dw1t1g.step / s-lmun5311dw1t1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (29 pp, sha256 baae4620958e523b, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF