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S-L2N7002KLT1G
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LRC MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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S-L2N7002KLT1G
LRC · MOSFETs · SOT-23
S-L2N7002KLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate terminal with ESD protection (2000 V HBM); gate-source voltage limited to ±20 V, threshold 1.0 to 2.5 V at 250 µA. |
| 2 | Source | passive | Source terminal of the N-channel MOSFET, with body diode continuous source current limited to 300 mA. |
| 3 | Drain | passive | Drain terminal with 60 V maximum drain-source voltage, 320 mA continuous drain current at 25°C and 1.5 A pulsed. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | 60 | Vdc | VGS = 0, ID = 250 μAdc | 2 | ||
| Gate Threshold Voltage | VGS(th) | 1 | Vdc | VDS = VGS, ID = 250 μAdc | 2 | ||
| Negative Threshold Temperature Coefficient | VGS(th)/TJ | 4 | mV/°C | 2 | |||
| Forward Transconductance | gfs | 80 | mS | VDS = 5.0 Vdc, ID = 200 mAdc | 2 | ||
| Drain-Source Voltage | VDSS | 60 | Vdc | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | Vdc | 1 | ||
| Drain Current, steady state | ID | 380 | mAdc | TA = 25°C, steady state | 1 | ||
| Drain Current, steady state | ID | 270 | mAdc | TA = 85°C, steady state | 1 | ||
| Pulsed Drain Current | IDM | 1.5 | A | tp = 10 μs | 1 | ||
| Source Current (Body Diode) | IS | 300 | mAdc | 1 | |||
| Junction and Storage Temperature | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Lead Temperature for Soldering Purposes | TL | 260 | °C | 1/8 in from case for 10 s | 1 | ||
| Gate-Source ESD Rating | ESD HBM | 2000 | V | HBM, Method 3015 | 1 | ||
| Total Device Dissipation, steady state | PD | 300 | mW | FR-5 board, 1.0 x 0.75 x 0.062 in, steady state | 1 | ||
| Total Device Dissipation, t<5s | PD | 420 | mW | FR-5 board, t<5s | 1 | ||
| Junction-to-Ambient, steady state | RθJA | 417 | °C/W | FR-5 board, steady state | 1 | ||
| Junction-to-Ambient, t<5s | RθJA | 300 | °C/W | FR-5 board, t<5s | 1 |
CAD (KiCad official)
- Symbol:
S-L2N7002KLT1G - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
s-l2n7002klt1g-etched.step/s-l2n7002klt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);s-l2n7002klt1g.step/s-l2n7002klt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (6 pp, sha256
fff7d3bd8264ede0, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# S-L2N7002KLT1G
**LRC** · MOSFETs · SOT-23
S-L2N7002KLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate terminal with ESD protection (2000 V HBM); gate-source voltage limited to ±20 V, threshold 1.0 to 2.5 V at 250 µA. |
| 2 | Source | passive | Source terminal of the N-channel MOSFET, with body diode continuous source current limited to 300 mA. |
| 3 | Drain | passive | Drain terminal with 60 V maximum drain-source voltage, 320 mA continuous drain current at 25°C and 1.5 A pulsed. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | V(BR)DSS | 60 | | | Vdc | VGS = 0, ID = 250 μAdc | 2 |
| Gate Threshold Voltage | VGS(th) | 1 | | | Vdc | VDS = VGS, ID = 250 μAdc | 2 |
| Negative Threshold Temperature Coefficient | VGS(th)/TJ | | 4 | | mV/°C | | 2 |
| Forward Transconductance | gfs | 80 | | | mS | VDS = 5.0 Vdc, ID = 200 mAdc | 2 |
| Drain-Source Voltage | VDSS | | | 60 | Vdc | | 1 |
| Gate-Source Voltage | VGS | -20 | | 20 | Vdc | | 1 |
| Drain Current, steady state | ID | | | 380 | mAdc | TA = 25°C, steady state | 1 |
| Drain Current, steady state | ID | | | 270 | mAdc | TA = 85°C, steady state | 1 |
| Pulsed Drain Current | IDM | | | 1.5 | A | tp = 10 μs | 1 |
| Source Current (Body Diode) | IS | | | 300 | mAdc | | 1 |
| Junction and Storage Temperature | TJ, Tstg | -55 | | 150 | °C | | 1 |
| Lead Temperature for Soldering Purposes | TL | | | 260 | °C | 1/8 in from case for 10 s | 1 |
| Gate-Source ESD Rating | ESD HBM | | | 2000 | V | HBM, Method 3015 | 1 |
| Total Device Dissipation, steady state | PD | | | 300 | mW | FR-5 board, 1.0 x 0.75 x 0.062 in, steady state | 1 |
| Total Device Dissipation, t<5s | PD | | | 420 | mW | FR-5 board, t<5s | 1 |
| Junction-to-Ambient, steady state | RθJA | | | 417 | °C/W | FR-5 board, steady state | 1 |
| Junction-to-Ambient, t<5s | RθJA | | | 300 | °C/W | FR-5 board, t<5s | 1 |
## CAD (KiCad official)
- Symbol: `S-L2N7002KLT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `s-l2n7002klt1g-etched.step` / `s-l2n7002klt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `s-l2n7002klt1g.step` / `s-l2n7002klt1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603136454318956544) (6 pp, sha256 `fff7d3bd8264ede0`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/s-l2n7002klt1g-datasheet.pdf)