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RT9026GSP

Public Made by Adom

by adom

Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs rt9026gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md rt9026gsp: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago
rt9026gsp-etched.fit.json rt9026gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
rt9026gsp-etched.glb rt9026gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
rt9026gsp-etched.step rt9026gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
rt9026gsp.glb fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.15x2.15mm, land 2.29x3.0mm (Δ0.99mm)) · Ray 1mo ago
rt9026gsp.kicad_mod fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.15x2.15mm, land 2.29x3.0mm (Δ0.99mm)) · Ray 1mo ago
rt9026gsp.kicad_sym Publish 0.1.0 · Ray 1mo ago
rt9026gsp.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 8 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
rt9026gsp.step fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.15x2.15mm, land 2.29x3.0mm (Δ0.99mm)) · Ray 1mo ago

RT9026GSP

Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP

RT9026GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground. Shared with pin 9 (exposed pad). The exposed pad must be soldered to a large PCB ground for maximum power dissipation.
2 S3 input Active-low Suspend-to-RAM mode control pin. When low, VTT is turned off and left High-Z while VTTREF remains active. Logic thresholds: VIH ≥ 1.6V, VIL ≤ 0.4V.
3 VTTSNS input VTT voltage sense input pin. Connect to the plus terminal of the VTT output capacitor for remote sensing of the VTT rail.
4 VTTREF output Buffered reference output equal to VDDQSNS/2 (e.g. 1.25/0.9/0.75/0.675/0.6 V). 10mA source/sink capability; ±20mV output tolerance; source current limit typ. 40mA.
5 VDDQSNS input VLDOIN (VDDQ) sense input pin. Divided internally by 2 to set the VTT and VTTREF target voltage. Input current typ. 50µA. Absolute max 3.6V.
6 VIN power_in Analog input pin to the control loop. Operating range 3.15V to 5.5V; absolute max 6V. UVLO rising threshold ≤ 2.7V with 0.2V hysteresis.
7 VLDOIN power_in Power supply of the VTT and VTTREF output stage (to power the internal MOSFETs). Operating range 1.2V to 3.3V; absolute max 3.6V.
8 VTT power_out Output voltage for connection to termination resistors, regulated to VDDQSNS/2. Sink/source up to 3A; ±20mV tolerance under load.
9 GND power_in Exposed thermal pad. Must be soldered to a large PCB ground plane for maximum power dissipation; electrically tied to pin 1 GND.

Key specifications

Parameter Value
Manufacturer Richtek Tech
Package SOP-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • RT9026GSPPSP
  • RT9026GSP
  • RT9026GSPPFP
  • RT9026GSPGFP
  • RT9026GSPPQW
  • RT9026GSPGQW

CAD (KiCad official)

  • Symbol: RT9026GSP
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: rt9026gsp-etched.step / rt9026gsp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rt9026gsp.step / rt9026gsp.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
rt9026gsp.step 125 KB You want the bare part, or you mark your own boards.
rt9026gsp-etched.step 2.3 MB You want the part with RT9026GSP already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 555 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Richtek Tech datasheet (14 pp, sha256 c00b245be9492010, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF