component
RT8072GSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT8072GSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT8072GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Compensation node; the external RC/CC network connected here sets the loop compensation. |
| 2 | GND | power_in | Analog ground; layout guidance returns small-signal components to GND at one point connected to PGND close to the IC. |
| 3 | EN | input | Chip enable: drive high (>1.5V, <5.5V) to enable and low (<0.4V) to shut down, and it is internally pulled up to high when floating. |
| 4 | VIN | power_in | Power input with a 2.9V to 5.5V recommended supply range and a −0.3V to 6.5V absolute maximum rating. |
| 5 | BOOT | power_in | Bootstrap supply for the high-side gate driver; BOOT to LX must stay within −0.3V to 6V. |
| 6 | LX | output | Switch node connecting the internal power MOSFETs to the inductor, with high-frequency voltage swing that should be kept in a small, short-trace area. |
| 7 | RT | passive | Frequency setting: an external resistor to GND sets the switching frequency from 300kHz to 2MHz, and a floating pin gives 300kHz. |
| 8 | FB | input | Feedback voltage input, connected to the resistor divider between VOUT and GND to regulate against the 0.8V ±1% reference. |
| 9 | PGND | power_in | Power ground (exposed pad); the exposed pad must be soldered to a large PCB area connected to PGND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage | VIN | 2.9 | 5.5 | V | 5 | ||
| Junction Temperature Range | -40 | 125 | °C | 5 | |||
| Ambient Temperature Range | -40 | 85 | °C | 5 | |||
| Supply Input Voltage | VIN | -0.3 | 6.5 | V | 5 | ||
| BOOT to LX | -0.3 | 6 | V | 5 | |||
| Other Pins (upper limit printed as VIN + 0.3V) | -0.3 | V | 5 | ||||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | Soldering, 10 sec. | 5 | |||
| Junction Temperature | 150 | °C | 5 | ||||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 5 | |||
| Power Dissipation PD (SOP-8 Exposed Pad) | PD | 2.041 | W | TA = 25°C, SOP-8 (Exposed Pad) | 5 | ||
| Under Voltage Lockout Threshold | VUVLO | 2.6 | 2.8 | V | VIN Rising | 5 | |
| Shutdown Current | ISHDN | 2 | 5 | µA | 5 | ||
| Voltage Reference | VREF | 0.792 | 0.8 | 0.808 | V | 5 | |
| Enable Logic-High | VIH | 1.5 | 5.5 | V | 5 | ||
| Enable Logic-Low | VIL | 0.4 | V | 5 | |||
| Switching Frequency Setting range | fOSC | 300 | 2000 | kHz | 5 | ||
| Current Limit Threshold | 6 | 8 | A | 6 | |||
| Package Thermal Resistance θJA | θJA | 49 | °C/W | SOP-8 (Exposed Pad) | 5 | ||
| Package Thermal Resistance θJC | θJC | 15 | °C/W | SOP-8 (Exposed Pad) | 5 |
CAD (KiCad official)
- Symbol:
RT8072GSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt8072gsp-etched.step/rt8072gsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8072gsp.step/rt8072gsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (16 pp, sha256
0f452d39d45a6808, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT8072GSP
**Richtek Tech** · DC-DC Converters · SOP-8-EP
RT8072GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMP | passive | Compensation node; the external RC/CC network connected here sets the loop compensation. |
| 2 | GND | power_in | Analog ground; layout guidance returns small-signal components to GND at one point connected to PGND close to the IC. |
| 3 | EN | input | Chip enable: drive high (>1.5V, <5.5V) to enable and low (<0.4V) to shut down, and it is internally pulled up to high when floating. |
| 4 | VIN | power_in | Power input with a 2.9V to 5.5V recommended supply range and a −0.3V to 6.5V absolute maximum rating. |
| 5 | BOOT | power_in | Bootstrap supply for the high-side gate driver; BOOT to LX must stay within −0.3V to 6V. |
| 6 | LX | output | Switch node connecting the internal power MOSFETs to the inductor, with high-frequency voltage swing that should be kept in a small, short-trace area. |
| 7 | RT | passive | Frequency setting: an external resistor to GND sets the switching frequency from 300kHz to 2MHz, and a floating pin gives 300kHz. |
| 8 | FB | input | Feedback voltage input, connected to the resistor divider between VOUT and GND to regulate against the 0.8V ±1% reference. |
| 9 | PGND | power_in | Power ground (exposed pad); the exposed pad must be soldered to a large PCB area connected to PGND for maximum power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage | VIN | 2.9 | | 5.5 | V | | 5 |
| Junction Temperature Range | | -40 | | 125 | °C | | 5 |
| Ambient Temperature Range | | -40 | | 85 | °C | | 5 |
| Supply Input Voltage | VIN | -0.3 | | 6.5 | V | | 5 |
| BOOT to LX | | -0.3 | | 6 | V | | 5 |
| Other Pins (upper limit printed as VIN + 0.3V) | | -0.3 | | | V | | 5 |
| Lead Temperature (Soldering, 10 sec.) | | | | 260 | °C | Soldering, 10 sec. | 5 |
| Junction Temperature | | | | 150 | °C | | 5 |
| Storage Temperature Range | | -65 | | 150 | °C | | 5 |
| ESD Susceptibility HBM | | | | 2 | kV | HBM (Human Body Model) | 5 |
| Power Dissipation PD (SOP-8 Exposed Pad) | PD | | | 2.041 | W | TA = 25°C, SOP-8 (Exposed Pad) | 5 |
| Under Voltage Lockout Threshold | VUVLO | | 2.6 | 2.8 | V | VIN Rising | 5 |
| Shutdown Current | ISHDN | | 2 | 5 | µA | | 5 |
| Voltage Reference | VREF | 0.792 | 0.8 | 0.808 | V | | 5 |
| Enable Logic-High | VIH | 1.5 | | 5.5 | V | | 5 |
| Enable Logic-Low | VIL | | | 0.4 | V | | 5 |
| Switching Frequency Setting range | fOSC | 300 | | 2000 | kHz | | 5 |
| Current Limit Threshold | | 6 | 8 | | A | | 6 |
| Package Thermal Resistance θJA | θJA | | 49 | | °C/W | SOP-8 (Exposed Pad) | 5 |
| Package Thermal Resistance θJC | θJC | | 15 | | °C/W | SOP-8 (Exposed Pad) | 5 |
## CAD (KiCad official)
- Symbol: `RT8072GSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt8072gsp-etched.step` / `rt8072gsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt8072gsp.step` / `rt8072gsp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8597529447122030592) (16 pp, sha256 `0f452d39d45a6808`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt8072gsp-datasheet.pdf)