RT6543AGQW

{
  "slug": "rt6543agqw",
  "version": "0.1.0",
  "type": "component",
  "description": "Richtek Tech AC-DC Controllers And Regulators, QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "rt6543agqw",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
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    "rt6543agqw.kicad_mod",
    "rt6543agqw.glb",
    "rt6543agqw.step",
    "rt6543agqw.lbr",
    "docs/hero.png",
    "docs/rt6543agqw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
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    "rt6543agqw-hero.overlay.json",
    "rt6543agqw-etched.glb"
  ],
  "component": {
    "mpn": "RT6543AGQW",
    "manufacturer": "Richtek Tech",
    "package": "QFN-20-EP(3x3)",
    "pin_count": 21,
    "category": "Power Management (PMIC)",
    "subcategory": "AC-DC Controllers And Regulators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603047792366022656",
    "parts": {
      "symbol": "rt6543agqw.kicad_sym",
      "footprint": "rt6543agqw.kicad_mod",
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      "model_3d_plain": "rt6543agqw-etched.glb",
      "model_3d_step": "rt6543agqw-etched.step",
      "model_3d_step_plain": "rt6543agqw.step",
      "lbr": "rt6543agqw.lbr"
    },
    "distributor_links": {
      "lcsc": "C3249953"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T18:42:15Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CS_DIS",
        "type": "passive",
        "description": "Current-limit setting pin: a resistor from CS to AGND sets the overcurrent limit, with a 6A typical CS source current at TA = 25°C and VCS limited to 0.5V to 2.8V over the operating temperature range."
      },
      {
        "number": "2",
        "name": "ISENSEP",
        "type": "input",
        "description": "Positive input for buck current sensing, shorted to ISENSEN for a zero load-line setting."
      },
      {
        "number": "3",
        "name": "ISENSEN",
        "type": "input",
        "description": "Negative input for buck current sensing, shorted to ISENSEP for a zero load-line setting."
      },
      {
        "number": "4",
        "name": "PGOOD",
        "type": "output",
        "description": "Open-drain power-good output for VCCIN_AUX that is pulled low during UVP, OVP, OTP, EN low, or when the output is not regulated, and requires an external pull-up of 10k to 100k."
      },
      {
        "number": "5",
        "name": "COMP",
        "type": "passive",
        "description": "Internal error amplifier output used for loop compensation."
      },
      {
        "number": "6",
        "name": "FB",
        "type": "input",
        "description": "Internal error amplifier input used for loop compensation."
      },
      {
        "number": "7",
        "name": "RGND",
        "type": "power_in",
        "description": "Return ground for VCCIN_AUX from the CPU side."
      },
      {
        "number": "8",
        "name": "VOUT",
        "type": "input",
        "description": "VCCIN_AUX feedback input used for AUX output regulation."
      },
      {
        "number": "9",
        "name": "FSWSEL",
        "type": "input",
        "description": "Switching-frequency setting pin: tie high to VCC, leave floating for the 600kHz default, or tie low to GND, and keep FSWSEL to VCC below 0.5V at all times."
      },
      {
        "number": "10",
        "name": "BOOT",
        "type": "power_out",
        "description": "Bootstrap capacitor node, charged through the low-side MOSFET conduction, that connects through a capacitor to PH to supply the high-side gate driver."
      },
      {
        "number": "11",
        "name": "UGATE",
        "type": "output",
        "description": "High-side gate driver output with sink and source capability, to be connected to the high-side MOSFET gate by a short, low-inductance path."
      },
      {
        "number": "12",
        "name": "PH",
        "type": "passive",
        "description": "AUX switch node connected to the power inductor and to the BOOT capacitor return; this noisy node must be kept away from sensitive traces."
      },
      {
        "number": "13",
        "name": "LGATE",
        "type": "output",
        "description": "Low-side gate driver output that must not have a series resistor to the low-side MOSFET gate, since LGATE is monitored for shoot-through protection."
      },
      {
        "number": "14",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground, connected to AGND at only one point through a short trace to reduce circulating currents."
      },
      {
        "number": "15",
        "name": "PVCC",
        "type": "power_in",
        "description": "Gate driver bias input with a 5V typical requirement that must be stable and filtered by an RC network (R = 2.2 and C = 1 F, 0603) placed as close as possible to the pin."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Control logic bias input with a 5V typical requirement that must be stable and filtered by an RC network (R = 2.2 and C = 1 F, 0603) placed as close as possible to the pin."
      },
      {
        "number": "17",
        "name": "VID1",
        "type": "input",
        "description": "VID control input that, together with VID0, sets the VCCIN_AUX output to 0V, 1.1V, 1.65V, or 1.8V."
      },
      {
        "number": "18",
        "name": "VID0",
        "type": "input",
        "description": "VID control input that, together with VID1, sets the VCCIN_AUX output to 0V, 1.1V, 1.65V, or 1.8V."
      },
      {
        "number": "19",
        "name": "EN",
        "type": "input",
        "description": "Enable input: below 0.3V puts the controller in shutdown with all power rails disabled, and above 1V wakes the controller."
      },
      {
        "number": "20",
        "name": "VSYS",
        "type": "input",
        "description": "System voltage sense input connected to the input voltage for UVLO monitoring and on-time setting, with an RC filter (R = 2.2 and C = 0.1 F, 0603) recommended to prevent noise disturbing the on-time."
      },
      {
        "number": "21",
        "name": "GND",
        "type": "power_in",
        "description": "Electrically isolated exposed pad that must be soldered to the large PGND plane with thermal vias to reduce thermal resistance."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package mapping: the hint says QFN-20-EP(3x3), but the datasheet names this part's package WQFN-20L ; Pin 1 name conflict: the pin table and block diagram label pin 1 'CS_DIS', but its function text des; Extraction lost symbols. The FSWSEL-to-VCC condition is printed as 'FSWSEL VCC < 0.5V' with the oper"
        ],
        "pages_sent": 4,
        "cost_usd": 0.0502,
        "at": "2026-10-17T18:37:45"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603047792366022656",
        "pages": 21,
        "sha256": "e77ca1eb744bcf71",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 21,
        "described": 21,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "0ee4e1082236390795238cd34b082d96efd160d6292c636cc40201a5a30cdc63",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "rt6543agqw-etched.step",
        "role": "eda",
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        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "7b1c24fc75824b4eb9ffc95e19a822b7f2c15f571f40a6a98a885dae47c531cb",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
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  }
}