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RT6543AGQW
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Richtek Tech AC-DC Controllers And Regulators, QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT6543AGQW
Richtek Tech · AC-DC Controllers And Regulators · QFN-20-EP(3x3)
RT6543AGQW from Richtek Tech, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS_DIS | passive | Current-limit setting pin: a resistor from CS to AGND sets the overcurrent limit, with a 6A typical CS source current at TA = 25°C and VCS limited to 0.5V to 2.8V over the operating temperature range. |
| 2 | ISENSEP | input | Positive input for buck current sensing, shorted to ISENSEN for a zero load-line setting. |
| 3 | ISENSEN | input | Negative input for buck current sensing, shorted to ISENSEP for a zero load-line setting. |
| 4 | PGOOD | output | Open-drain power-good output for VCCIN_AUX that is pulled low during UVP, OVP, OTP, EN low, or when the output is not regulated, and requires an external pull-up of 10k to 100k. |
| 5 | COMP | passive | Internal error amplifier output used for loop compensation. |
| 6 | FB | input | Internal error amplifier input used for loop compensation. |
| 7 | RGND | power_in | Return ground for VCCIN_AUX from the CPU side. |
| 8 | VOUT | input | VCCIN_AUX feedback input used for AUX output regulation. |
| 9 | FSWSEL | input | Switching-frequency setting pin: tie high to VCC, leave floating for the 600kHz default, or tie low to GND, and keep FSWSEL to VCC below 0.5V at all times. |
| 10 | BOOT | power_out | Bootstrap capacitor node, charged through the low-side MOSFET conduction, that connects through a capacitor to PH to supply the high-side gate driver. |
| 11 | UGATE | output | High-side gate driver output with sink and source capability, to be connected to the high-side MOSFET gate by a short, low-inductance path. |
| 12 | PH | passive | AUX switch node connected to the power inductor and to the BOOT capacitor return; this noisy node must be kept away from sensitive traces. |
| 13 | LGATE | output | Low-side gate driver output that must not have a series resistor to the low-side MOSFET gate, since LGATE is monitored for shoot-through protection. |
| 14 | PGND | power_in | Power ground, connected to AGND at only one point through a short trace to reduce circulating currents. |
| 15 | PVCC | power_in | Gate driver bias input with a 5V typical requirement that must be stable and filtered by an RC network (R = 2.2 and C = 1 F, 0603) placed as close as possible to the pin. |
| 16 | VCC | power_in | Control logic bias input with a 5V typical requirement that must be stable and filtered by an RC network (R = 2.2 and C = 1 F, 0603) placed as close as possible to the pin. |
| 17 | VID1 | input | VID control input that, together with VID0, sets the VCCIN_AUX output to 0V, 1.1V, 1.65V, or 1.8V. |
| 18 | VID0 | input | VID control input that, together with VID1, sets the VCCIN_AUX output to 0V, 1.1V, 1.65V, or 1.8V. |
| 19 | EN | input | Enable input: below 0.3V puts the controller in shutdown with all power rails disabled, and above 1V wakes the controller. |
| 20 | VSYS | input | System voltage sense input connected to the input voltage for UVLO monitoring and on-time setting, with an RC filter (R = 2.2 and C = 0.1 F, 0603) recommended to prevent noise disturbing the on-time. |
| 21 | GND | power_in | Electrically isolated exposed pad that must be soldered to the large PGND plane with thermal vias to reduce thermal resistance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | QFN-20-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Input Voltage (recommended operating) | VCC | 4.5 | 5.5 | V | 5 | ||
| VSYS Input Voltage (recommended operating) | VSYS | 3 | 24 | V | 5 | ||
| Junction Temperature Range (recommended operating) | TJ | -40 | 125 | °C | 5 | ||
| VSYS to PGND (absolute maximum) | VSYS | -0.3 | 28 | V | DC | 5 | |
| VCC to PGND (absolute maximum) | VCC | -0.3 | 6.5 | V | DC | 5 | |
| RGND to PGND (absolute maximum) | RGND | -0.3 | 0.3 | V | DC | 5 | |
| BOOT to PH (absolute maximum) | VBOOT-PH | -0.3 | 6.5 | V | DC | 5 | |
| BOOT to PH (absolute maximum) | VBOOT-PH | -2 | 7.5 | V | <100ns | 5 | |
| BOOT to PGND (absolute maximum) | VBOOT | -0.3 | 30 | V | DC | 5 | |
| BOOT to PGND (absolute maximum) | VBOOT | -10 | 35 | V | <100ns | 5 | |
| LGATE to PGND (absolute maximum) | VLGATE | -0.3 | 6.8 | V | DC | 5 | |
| LGATE to PGND (absolute maximum) | VLGATE | -2 | 7.5 | V | <100ns | 5 | |
| PH to PGND (absolute maximum) | VPH | -0.3 | 30 | V | DC | 5 | |
| PH to PGND (absolute maximum) | VPH | -10 | 35 | V | <100ns | 5 | |
| UGATE to PGND (absolute maximum) | VUGATE | -0.3 | 36.8 | V | DC | 5 | |
| UGATE to PGND (absolute maximum) | VUGATE | -10 | 41.8 | V | <100ns | 5 | |
| Other pins (absolute maximum) | -0.3 | 6.8 | V | 5 | |||
| Power Dissipation PD at TA = 25°C | PD | 3.33 | W | TA = 25°C, WQFN-20L 3x3 | 5 | ||
| Package Thermal Resistance junction-to-ambient | θJA | 30 | °C/W | WQFN-20L 3x3 | 5 | ||
| Package Thermal Resistance junction-to-case | θJC | 7.5 | °C/W | WQFN-20L 3x3 | 5 | ||
| Junction Temperature (absolute maximum) | TJ | 150 | °C | 5 | |||
| Lead Temperature (soldering) | 260 | °C | Soldering, 10 sec. | 5 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 5 | |||
| Supply Voltage VCC | VCC | 4.5 | 5 | 5.5 | V | 6 | |
| Supply Current IVCC | IVCC | 0.3 | 0.55 | mA | VEN = 5V, no switching | 6 | |
| VCC POR Threshold | VCC_POR | 4 | 4.2 | 4.4 | V | 6 | |
| VCC UVLO Threshold | VVCC_UVLO | 3.7 | 3.9 | 4.1 | V | 6 | |
| VID0/VID1 Input Low Voltage | VID_IL | 0.3 | V | Falling edge, VCC = 5V | 6 | ||
| VID0/VID1 Input High Voltage | VID_IH | 1 | V | Rising edge, VCC = 5V | 6 | ||
| EN Input Low Voltage | VEN_IL | 0.3 | V | Falling edge, VCC = 5V | 6 | ||
| EN Input High Voltage | VEN_IH | 1 | V | Rising edge, VCC = 5V | 6 | ||
| FSWSEL Input High Level | VFSWSEL_H | 4.5 | V | Rising edge, VCC = 5V | 6 | ||
| FSWSEL Input Low Level | VFSWSEL_L | 0.4 | V | Falling edge, VCC = 5V | 6 | ||
| FSWSEL Input Floating Level | VFSWSEL_HIZ | 2 | 2.5 | 3 | V | Floating, VCC = 5V | 6 |
| PGOOD High Threshold | VPGOOD_IH | 86 | 90 | 94 | %VOUT | Rising edge | 7 |
| PGOOD Low Threshold | VPGOOD_IL | 80 | 84 | 88 | %VOUT | Falling edge | 7 |
| PGOOD Leakage Current | ILK_PGOOD | 1 | µA | High state, VPGOOD = 5V | 7 | ||
| PGOOD Output Low Voltage | VPGOOD_LOW | 0.3 | V | IPGOOD_LOW = 10mA | 7 | ||
| Input Supply Voltage (VIN) | VIN | 3 | 24 | V | 7 | ||
| Output Voltage Scaling, VID[1:0] = 11 | VOUT | 1.782 | 1.8 | 1.818 | V | VID[1:0] = 11 | 7 |
| Output Voltage Scaling, VID[1:0] = 10 | VOUT | 1.6335 | 1.65 | 1.666 | V | VID[1:0] = 10 | 7 |
| Output Voltage Scaling, VID[1:0] = 01 | VOUT | 1.089 | 1.1 | 1.111 | V | VID[1:0] = 01 | 7 |
| Output Voltage Scaling, VID[1:0] = 00 | VOUT | 0.01 | 0 | 0.01 | V | VID[1:0] = 00 | 7 |
| Dynamic Voltage Scale Slew Rate | SRDVS | 12 | 40 | mV/s | 7 | ||
| Current Limit | ILIM | 5.4 | 6 | 6.6 | A | 7 | |
| Current Limit Setting Range (VCS) | VCS | 0.4 | 2.8 | V | Voltage of pin CS_DIS | 7 | |
| Current Limit Voltage tolerance, 0.5V ≤ VCS ≤ 2.8V | V_PHASW_OC | -15 | 15 | % | GND PHASE = VCS / 12, 0.5V ≤ VCS ≤ 2.8V | 7 | |
| Current Limit Voltage tolerance, 0.4V ≤ VCS ≤ 0.5V | V_PHASW_OC | -7 | 7 | mV | GND PHASE = VCS / 12, 0.4V ≤ VCS ≤ 0.5V | 7 | |
| Switching Frequency Accuracy | fSW | 0.51 | 0.6 | 0.69 | MHz | FSWSEL = HIZ | 7 |
| OVP Trip Threshold | VOVP | 2.05 | 2.2 | 2.35 | V | OVP detect | 8 |
| UVP Trip Threshold | VUVP | 48 | 60 | 72 | % | UVP detect | 8 |
| Zero Current Crossing Threshold | VPH_ZC | 4 | 4 | mV | 8 | ||
| UGATE Driver Source Resistance | RUGATEsr | 2 | 4 | Ω | BOOT - LX = 5V | 8 | |
| UGATE Driver Sink Resistance | RUGATEsk | 1 | 2 | Ω | BOOT - LX = 5V | 8 | |
| LGATE Driver Source Resistance | RLGATEsr | 1.5 | 3 | Ω | LGATE, high state, VCC = 5V | 8 | |
| LGATE Driver Sink Resistance | RLGATEsk | 0.7 | 3 | Ω | LGATE, low state, VCC = 5V | 8 | |
| Internal Boost Diode Resistance | RBOOT | 40 | 80 | Ω | VCC to BOOT, IBOOT = 10mA | 8 |
CAD (KiCad official)
- Symbol:
RT6543AGQW - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt6543agqw-etched.step/rt6543agqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6543agqw.step/rt6543agqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (21 pp, sha256
e77ca1eb744bcf71, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).