component
RT6252BHGJ6F
Public Made by Adomby adom
Richtek Tech DC-DC Converters, TSOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownRT6252BHGJ6F
Richtek Tech · DC-DC Converters · TSOT-23-6
RT6252BHGJ6F from Richtek Tech, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Power ground return for the IC and the low-side MOSFET source. |
| 2 | SW | power_out | Switch node between the internal high-side and low-side (synchronous rectifier) MOSFETs. Connect to the external inductor and to the bootstrap capacitor's low side. |
| 3 | VIN | power_in | Power input, 4.5V to 17V. Bypass directly to GND with an MLCC ≥ 20µF placed close to the pin. |
| 4 | FB | input | Feedback voltage input. Connect to the midpoint of the external resistor divider from VOUT to GND. Regulated to VFB ≈ 0.765V (±1%). |
| 5 | EN | input | Enable control input. Logic high enables the converter; tie to GND to disable. An internal REN_DN pulldown allows the pin to float to a shutdown state. |
| 6 | BOOT | power_in | Bootstrap capacitor node for the high-side gate driver. Connect a 0.1µF ceramic capacitor from BOOT to SW. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TSOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
RT6252BHGJ6FRT6252BHGJ6FH6FRT6252BHGJ6FHGH6F
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Operating Voltage | VIN | 4.5 | 17 | V | 8 | ||
| Under-Voltage Lockout Threshold | VUVLO | 3.7 | 4 | 4.3 | V | 8 | |
| Shutdown Current | ISHDN | 4 | µA | VEN = 0V | 8 | ||
| Enable Voltage Threshold, EN high-level input voltage | VEN_H | 1.16 | 1.25 | 1.34 | V | 8 | |
| Enable Voltage Threshold, EN low-level input voltage | VEN_L | 1.01 | 1.1 | 1.19 | V | 8 | |
| EN Pin Pull-Down Resistance | REN_DN | 225 | 450 | 900 | k | EN pin resistance to GND, VEN = 12V | 8 |
| Feedback Threshold Voltage | VFB | 758 | 765 | 772 | mV | VOUT = 1.05V | 8 |
| Feedback Input Current | IFB | -0.1 | 0 | 0.1 | A | VFB = 0.8V, TA = 25°C | 8 |
| Low-Side Switch Valley Current Limit | ILIM_L | 2.2 | 3.2 | 4.2 | A | 8 | |
| Minimum Off-Time | tOFF_MIN | 200 | 260 | ns | VFB = 0.5V | 8 | |
| Supply Input Operating Voltage | VIN | 4.5 | 17 | V | 7 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 7 | ||
| Supply Input Voltage | VIN | -0.3 | 20 | V | 7 | ||
| Enable Voltage | EN | -0.3 | 20 | V | 7 | ||
| Switch Voltage | SW | -0.3 | 20.3 | V | 7 | ||
| Switch Voltage (transient) | SW | -5 | 25 | V | < 100ns | 7 | |
| BOOT Voltage | BOOT | -0.3 | 26 | V | 7 | ||
| BOOT to SW Voltage | VBOOT - VSW | -0.3 | 6 | V | 7 | ||
| Feedback Voltage | FB | -0.3 | 6 | V | 7 | ||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 7 | |||
| Junction Temperature | 150 | °C | 7 | ||||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Junction-to-ambient thermal resistance (JEDEC standard) | θJA | 88.7 | °C/W | JEDEC standard, TSOT-23-6 (FC) | 7 | ||
| Junction-to-case (top) thermal resistance | θJC(Top) | 76.9 | °C/W | TSOT-23-6 (FC) | 7 | ||
| Junction-to-case (bottom) thermal resistance | θJC(Bottom) | 6 | °C/W | TSOT-23-6 (FC) | 7 | ||
| Junction-to-ambient thermal resistance (specific EVB) | θJA(EVB) | 63.3 | °C/W | specific EVB, TSOT-23-6 (FC) | 7 | ||
| Junction-to-top characterization parameter | JC(Top) | 15.3 | °C/W | TSOT-23-6 (FC) | 7 | ||
| Junction-to-board characterization parameter | JB | 34.66 | °C/W | TSOT-23-6 (FC) | 7 |
CAD (KiCad official)
- Symbol:
RT6252BHGJ6F - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
rt6252bhgj6f-etched.step/rt6252bhgj6f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6252bhgj6f.step/rt6252bhgj6f.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
rt6252bhgj6f.step |
97 KB | You want the bare part, or you mark your own boards. |
rt6252bhgj6f-etched.step |
2.5 MB | You want the part with RT6252BHGJ6F already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 590 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (31 pp, sha256
b3073e6d0c76ec40, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).