PY32F003L16S6TU

{
  "slug": "py32f003l16s6tu",
  "version": "0.1.0",
  "type": "component",
  "description": "PUYA Microcontrollers (MCU/MPU/SOC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "py32f003l16s6tu",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "py32f003l16s6tu.kicad_sym",
    "py32f003l16s6tu.kicad_mod",
    "py32f003l16s6tu.glb",
    "py32f003l16s6tu.step",
    "py32f003l16s6tu.lbr",
    "docs/hero.png",
    "docs/py32f003l16s6tu-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "py32f003l16s6tu-hero.glb",
    "py32f003l16s6tu-hero.overlay.json",
    "py32f003l16s6tu-etched.glb"
  ],
  "component": {
    "mpn": "PY32F003L16S6TU",
    "manufacturer": "PUYA",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835843285114880",
    "parts": {
      "symbol": "py32f003l16s6tu.kicad_sym",
      "footprint": "py32f003l16s6tu.kicad_mod",
      "model_3d": "py32f003l16s6tu-hero.glb",
      "model_3d_plain": "py32f003l16s6tu-etched.glb",
      "model_3d_step": "py32f003l16s6tu-etched.step",
      "model_3d_step_plain": "py32f003l16s6tu.step",
      "lbr": "py32f003l16s6tu.lbr"
    },
    "distributor_links": {
      "lcsc": "C5128435"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T03:15:50Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VCC",
        "type": "power_in",
        "description": "Digital power supply, 1.7V to 5.5V operating range."
      },
      {
        "number": "2",
        "name": "PA0",
        "type": "bidirectional",
        "description": "General-purpose I/O (COM 5V-type port) with USART1_CTS, COMP1_OUT, TIM1_CH3, TIM1_CH1N, SPI1_MISO, IR_OUT alternate functions and ADC_IN0, COMP1_INM additional functions."
      },
      {
        "number": "3",
        "name": "PA1",
        "type": "bidirectional",
        "description": "General-purpose I/O (COM port) with SPI1_SCK, USART1_RTS, EVENTOUT, SPI1_MOSI, TIM1_CH4, TIM1_CH2N, MCO alternate functions and ADC_IN1, COMP1_INP additional functions."
      },
      {
        "number": "4",
        "name": "PA2",
        "type": "bidirectional",
        "description": "General-purpose I/O (COM port) with SPI1_MOSI, USART1_TX, SPI1_SCK, TIM3_CH1, I2C_SDA alternate functions and ADC_IN2 additional function."
      },
      {
        "number": "5",
        "name": "PF2-NRST / PB0",
        "type": "bidirectional",
        "description": "PF2 or NRST (reset port with internal weak pull-up, selected via option bytes; MCO alternate function) shared with PB0 (SPI1_NSS, TIM3_CH3, TIM1_CH2N, EVENTOUT, COMP1_OUT, ADC_IN8); only one of the two IOs usable at a time, the other must be in analog mode."
      },
      {
        "number": "6",
        "name": "PA10 / PA13(SWDIO)",
        "type": "bidirectional",
        "description": "PA10 (USART1_RX, TIM1_CH3, TIM17_BKIN, I2C_SDA, I2C_SCL, SPI1_NSS, USART1_TX, IR_OUT, EVENTOUT) shared with PA13 SWDIO (internal pull-up active after reset; IR_OUT, SPI1_MISO, TIM1_CH2, USART1_RX, MCO); only one IO usable at a time."
      },
      {
        "number": "7",
        "name": "PA14(SWCLK) / PB5",
        "type": "bidirectional",
        "description": "PA14 SWCLK (internal pull-down active after reset; USART1_TX, EVENTOUT, MCO) shared with PB5 (SPI1_MOSI, TIM3_CH2, TIM16_BKIN, USART1_CK, LPTIM_IN1, COMP1_OUT); only one IO usable at a time."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground pin; the pin table lists pin 8 as 'VCC' but the pinout figure shows a GND pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The SOP8 pin table lists no pin number for GND, although Figure 4-1 shows a GND pad between PA2 and ; Pins 6 and 7 are ambiguous. Table 4-2 and its footnote (3) say PB0, PA10 and PB5 share one physical ; Pin 5 is printed as I/O type with RST port structure and is selected between PF2 and NRST by option "
        ],
        "pages_sent": 23,
        "cost_usd": 0.0988,
        "at": "2026-10-18T03:15:10"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589835843285114880",
        "pages": 39,
        "sha256": "a4f4303cf7c19726",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "py32f003l16s6tu.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "py32f003l16s6tu-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "314e54698b22602282fd440208c8ea62de8eaf3e4183b41056a91342df87f676",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}