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PTH12050WAD

Texas Instruments · Power Modules · DIP-6

PTH12050WAD from Texas Instruments, in a DIP-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Common ground connection for the VI and VO power connections and the 0-VDC reference for the control inputs.
2 Track input Analog input that lets the output follow an external voltage volt-for-volt from 0 V up to the set-point, becomes active typically 20 ms after VI is applied, and should be connected to VI if unused.
3 VI power_in Positive input voltage power node referenced to GND, with a 10.8 V to 13.2 V input range over the IO range and undervoltage lockout between 8.8 V and 10.4 V.
4 Inhibit input Open-collector/drain negative-logic input referenced to GND that disables the output when driven low (VIL −0.2 V to 0.5 V), and must not have an external pull-up.
5 VO Adjust passive A 1% resistor (100 ppm/°C or better) connected directly between this pin and GND (pin 1) sets the output voltage above its lowest value, with the set-point range 1.2 V to 5.5 V for W-suffix devices and 0.8 V to 1.8 V for L-suffix devices, and an open circuit defaulting to the lowest value.
6 VO power_out Regulated positive power output referenced to GND, adjustable over 1.2 V to 5.5 V for W-suffix devices with output current up to 6 A.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-6
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output current IO 0 6 A 85°C, 400 LFM airflow; over ΔVadj range 3
Output current IO 6 A 60°C, natural convection 3
Input voltage range VI 10.8 13.2 V Over IO range 3
Set-point voltage tolerance Vo tol -2 2 %Vo 3
Temperature variation ΔRegtemp -0.5 0.5 %Vo -40°C < TA < 85°C 3
Line regulation ΔRegline -5 5 mV Over VI range 3
Load regulation ΔRegload -5 5 mV Over IO range 3
Total output variation ΔRegtot -3 3 %Vo Includes set-point, line, load, -40°C ≤ TA ≤ 85°C 3
Output voltage adjust range ΔVadj 1.2 5.5 V Over VI range 3
VO ripple (peak-to-peak) Vr 25 mVpp VO ≤ 2.5 V; 20-MHz bandwidth 3
VO ripple (peak-to-peak) Vr 1 %Vo VO > 2.5 V; 20-MHz bandwidth 3
Under-voltage lockout, increasing UVLO 9.5 10.4 V VI increasing 3
Under-voltage lockout, decreasing UVLO 8.8 9 V VI decreasing 3
Input low voltage (inhibit control, pin 4) VIL -0.2 0.5 V Referenced to GND 3
Switching frequency fs 260 320 380 kHz Over VI and IO ranges 3
Transient response overshoot/undershoot ΔVtr 100 mV Transient response 50 to 100% IOmax, C3 = 100 µF 3
Track slew rate capability dVtrack/dt 1 V/ms CO ≤ CO(max) 3
External input capacitance, C1 C1 100 µF 3
External output capacitance, C3 (nonceramic) C3 0 100 3300 µF Nonceramic 3
External output capacitance, C3 (ceramic) C3 0 300 µF Ceramic 3
Track pin voltage -0.3 V Track input voltage; upper limit printed as VI+0.3 V 2
Operating temperature range TA -40 85 °C Over VI range 2
Storage temperature Tstg -55 125 °C 2

CAD (KiCad official)

  • Symbol: PTH12050WAD
  • Footprint: Package_DIP:DIP-6_W7.62mm
  • 3D model: DIP-6 (KiCad packages3D, STEP)
  • 3D model files: pth12050wad-etched.step / pth12050wad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pth12050wad.step / pth12050wad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 499b9c729705c05e, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF