PMDT670UPE

{
  "schema_version": 1,
  "type": "component",
  "slug": "pmdt670upe",
  "title": "PMDT670UPE",
  "brief": "Nexperia MOSFETs, SOT-666. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "transistors-thyristors",
    "pmdt670upe"
  ],
  "component": {
    "mpn": "PMDT670UPE",
    "manufacturer": "Nexperia",
    "package": "SOT-666",
    "pin_count": 6,
    "category": "Transistors/Thyristors",
    "subcategory": "MOSFETs",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914955852107776",
    "parts": {
      "symbol": "pmdt670upe.kicad_sym",
      "footprint": "pmdt670upe.kicad_mod",
      "model_3d": "pmdt670upe-etched.glb",
      "model_3d_plain": "pmdt670upe.glb",
      "model_3d_step": "pmdt670upe-etched.step",
      "model_3d_step_plain": "pmdt670upe.step",
      "lbr": "pmdt670upe.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "S1",
        "type": "passive",
        "description": "Source of transistor TR1 (P-channel MOSFET #1). Typically tied to the higher potential rail in a P-channel high-side switch configuration."
      },
      {
        "number": "2",
        "name": "G1",
        "type": "input",
        "description": "Gate of transistor TR1. VGS threshold voltage typically -0.8 V (spec -0.5 V to -1.3 V); absolute maximum VGS ±8 V."
      },
      {
        "number": "3",
        "name": "D2",
        "type": "passive",
        "description": "Drain of transistor TR2 (P-channel MOSFET #2). Absolute maximum VDS = -20 V; continuous ID = -550 mA at Tamb = 25 °C."
      },
      {
        "number": "4",
        "name": "S2",
        "type": "passive",
        "description": "Source of transistor TR2 (P-channel MOSFET #2)."
      },
      {
        "number": "5",
        "name": "G2",
        "type": "input",
        "description": "Gate of transistor TR2. Same drive characteristics as G1 (VGSth typ -0.8 V; VGS abs max ±8 V)."
      },
      {
        "number": "6",
        "name": "D1",
        "type": "passive",
        "description": "Drain of transistor TR1 (P-channel MOSFET #1). Absolute maximum VDS = -20 V; continuous ID = -550 mA at Tamb = 25 °C."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914955852107776",
        "pages": 14,
        "sha256": "90d312c8a44e8094",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 6,
        "described": 6,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pmdt670upe.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          1.6,
          1.6,
          0.55
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "eeaa97c06a9396d5faa21f9016c75f498a547b5ab955a64686d4a98199667adf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pmdt670upe-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          1.6,
          1.6,
          0.55
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f19f523371852e78350fd16d71e4e41f8aef1e0d08a92d420c2fe48851eda454",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Nexperia",
      "Package": "SOT-666",
      "Category": "Transistors/Thyristors",
      "Pins": "6"
    }
  },
  "variants": [
    {
      "mpn": "PMDT670UPE",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "pmdt670upe"
  ],
  "discovery_pitch": "PMDT670UPE (Nexperia) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pmdt670upe.kicad_sym",
    "pmdt670upe.kicad_mod",
    "pmdt670upe.glb",
    "pmdt670upe.step",
    "pmdt670upe.lbr",
    "docs/hero.png",
    "docs/pmdt670upe-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-25T04:28:56.381Z"
}