component

PMDT670UPE

Public Made by Adom

by adom

Nexperia MOSFETs, SOT-666. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorspmdt670upe
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs pmdt670upe: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pmdt670upe: viewers · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json pmdt670upe: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
pmdt670upe-etched.fit.json pmdt670upe: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
pmdt670upe-etched.glb pmdt670upe: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
pmdt670upe-etched.step pmdt670upe: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
pmdt670upe.glb Publish 0.1.0 · Ray 1mo ago
pmdt670upe.kicad_mod Publish 0.1.0 · Ray 1mo ago
pmdt670upe.kicad_sym Publish 0.1.0 · Ray 1mo ago
pmdt670upe.lbr Publish 0.1.0 · Ray 1mo ago
pmdt670upe.step Publish 0.1.0 · Ray 1mo ago
README.md pmdt670upe: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

PMDT670UPE

Nexperia · MOSFETs · SOT-666

PMDT670UPE from Nexperia, in a SOT-666. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of transistor TR1 (P-channel MOSFET #1). Typically tied to the higher potential rail in a P-channel high-side switch configuration.
2 G1 input Gate of transistor TR1. VGS threshold voltage typically -0.8 V (spec -0.5 V to -1.3 V); absolute maximum VGS ±8 V.
3 D2 passive Drain of transistor TR2 (P-channel MOSFET #2). Absolute maximum VDS = -20 V; continuous ID = -550 mA at Tamb = 25 °C.
4 S2 passive Source of transistor TR2 (P-channel MOSFET #2).
5 G2 input Gate of transistor TR2. Same drive characteristics as G1 (VGSth typ -0.8 V; VGS abs max ±8 V).
6 D1 passive Drain of transistor TR1 (P-channel MOSFET #1). Absolute maximum VDS = -20 V; continuous ID = -550 mA at Tamb = 25 °C.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOT-666
Category Transistors/Thyristors
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • PMDT670UPE

CAD (KiCad official)

  • Symbol: PMDT670UPE
  • Footprint: Package_TO_SOT_SMD:SOT-666
  • 3D model: SOT-666 (KiCad packages3D, STEP)
  • 3D model files: pmdt670upe-etched.step / pmdt670upe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pmdt670upe.step / pmdt670upe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 90d312c8a44e8094, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF