component
PL82052
Public Made by Adomby adom
POWLICON DC-DC Converters, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 8d ago |
| viewers | 8d ago |
| package.json | 8d ago |
| page.json | 8d ago |
| pl82052-etched.glb | 8d ago |
| pl82052-etched.step | 8d ago |
| pl82052-hero.glb | 8d ago |
| pl82052-hero.overlay.json | 8d ago |
| pl82052.glb | 8d ago |
| pl82052.kicad_mod | 8d ago |
| pl82052.kicad_sym | 8d ago |
| pl82052.lbr | 8d ago |
| pl82052.step | 8d ago |
| README.md | 8d ago |
PL82052
POWLICON · DC-DC Converters · ESOP-8
PL82052 from POWLICON, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | passive | Boot-strap pin: connect a 0.1µF or greater capacitor between SW and BST to power the high-side gate driver; BST to SW is limited to -0.3 to 6.5 V (absolute maximum) and the datasheet recommends 0 to SW+5 V. |
| 2 | VIN | power_in | Power input that supplies the IC; supply with 4.6 V to 33 V (absolute maximum VIN to GND is -0.3 to +40 V) and bypass to GND with a large capacitor plus at least 0.1 µF ceramic placed close to VIN and GND. |
| 3 | ROSC | passive | Switching frequency program pin: connect a resistor to set the frequency (80 kHz to 2 MHz range), or leave open for 160 kHz switching frequency; absolute maximum is -0.3 to +6.5 V. |
| 4 | SS | passive | Soft-start pin: an external capacitor connected to this pin sets the output rise time, with a 2 µA internal charge current and a recommended slow-start time of 10 ms to 100 ms; the SS voltage is limited to 0 to 5 V. |
| 5 | FB | input | Output voltage feedback pin; the internal reference is 0.8 V (±1.5% initial accuracy) and FB voltage is limited to 0 to 5 V. |
| 6 | COMP | passive | Error amplifier output and input to the PWM comparator; connect frequency compensation components to this pin, with voltage limited to 0 to 5 V. |
| 7 | GND | power_in | Ground pin; connect input and output capacitor grounds to this pin and the PAD through localized top-side planes. |
| 8 | SW | output | Power switching pin connected to the inductor switching node; SW to GND absolute maximum is -0.3 to +40 V and the recommended range is 0 to 33 V. |
| 9 | GND | power_in | Listed in the pin table as a second ground pin ("7,9 GND"); the layout section refers to the GND pin and PAD, so this is likely the exposed thermal pad. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | POWLICON |
| Package | ESOP-8 |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND voltage | VIN | -0.3 | 40 | V | 3 | ||
| BST to SW voltage | BST | -0.3 | 6.5 | V | 3 | ||
| SW to GND voltage | SW | -0.3 | 40 | V | 3 | ||
| ROSC, SS, FB, COMP voltage | ROSC, SS, FB, COMP | -0.3 | 6.5 | V | 3 | ||
| Storage Temperature Range | TST | -65 | 150 | °C | 3 | ||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Lead Temperature | TL | 260 | °C | 3 | |||
| ESD HBM | VESD | 2 | kV | Human body model | 3 | ||
| VIN Voltage | VIN | 5 | 33 | V | 3 | ||
| SW Voltage | SW | 0 | 33 | V | 3 | ||
| BST Voltage | BST | 0 | V | 3 | |||
| ROSC Voltage | ROSC | 0.4 | 0.6 | V | 3 | ||
| FB voltage | FB | 0 | 5 | V | 3 | ||
| SS, COMP Voltage | SS, COMP | 0 | 5 | V | 3 | ||
| Operating Ambient Temperature Range | TA | -40 | 125 | °C | 3 | ||
| Buck input standoff voltage | VIN_max | 40 | V | 4 | |||
| Buck input voltage range | VIN | 4.6 | 33 | V | VIN = 12 V, TJ = -40 °C to 125 °C | 4 | |
| Buck switching frequency range | Fbuck | 80 | 2000 | kHz | Set by external resistor ROSC | 4 | |
| Frequency spread spectrum in percentage of Fbuck | fjitter | -6 | 6 | % | 4 | ||
| FB voltage | FB | 0.788 | 0.8 | 0.812 | V | 4 | |
| VIN UVLO voltage, VIN rising | VIN_UVLO | 4.6 | V | VIN rising | 4 | ||
| VIN UVLO voltage, VIN falling | VIN_UVLO | 4.1 | V | VIN falling | 4 | ||
| VIN over voltage, VIN rising | VIN_OVP | 33 | V | VIN rising | 4 | ||
| VIN over voltage, VIN falling | VIN_OVP | 30 | V | VIN falling | 4 | ||
| Programmable frequency | fSW_BK | 160 | kHz | ROSC = OPEN | 4 | ||
| Programmable frequency | fSW_BK | 80 | kHz | ROSC = GND | 4 | ||
| Maximum Duty Cycle | Dmax | 98 | % | 4 | |||
| Minimum On Time | Ton | 100 | ns | 4 | |||
| Peak inductor current limit | ILIMIT | 6.5 | A | 4 | |||
| Soft Start charge current | ISS | 2 | μA | 4 | |||
| High-Side Switch On-Resistance | RDS(ON)_H | 80 | mΩ | 4 | |||
| Low-Side Switch On-Resistance | RDS(ON)_L | 50 | mΩ | 4 | |||
| Thermal Shutdown | Thsd | 160 | ℃ | 4 | |||
| Thermal Shutdown Hysteresis | Thsdhys | 60 | ℃ | 4 | |||
| Junction to ambient thermal resistance | θJA | 56 | °C/W | 3 | |||
| Junction to case thermal resistance | θJC | 45 | °C/W | 3 |
CAD (KiCad official)
- Symbol:
PL82052 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
pl82052-etched.step/pl82052-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pl82052.step/pl82052.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: POWLICON datasheet (14 pp, sha256
3504e54833c78b06, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).