component
PIC18F26K42-I
Public Made by Adomby adom
Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"version": "0.1.0",
"type": "component",
"description": "Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"single chip microcomputer-microcontroller",
"pic18f26k42-i",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
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"pic18f26k42-i.step",
"pic18f26k42-i.lbr",
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"docs/pic18f26k42-i-datasheet.pdf",
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"component": {
"mpn": "PIC18F26K42-I",
"manufacturer": "Microchip Tech",
"package": "SOIC-28-300mil",
"pin_count": 28,
"category": "Single Chip Microcomputer/Microcontroller",
"subcategory": "Microcontroller Units (MCUs/MPUs/SOCs)",
"datasheet": "https://ww1.microchip.com/downloads/en/DeviceDoc/PIC18(L)F26-27-45-46-47-55-56-57K42-Data-Sheet-40001919G.pdf",
"parts": {
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"footprint": "pic18f26k42-i.kicad_mod",
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"lbr": "pic18f26k42-i.lbr"
},
"distributor_links": {
"lcsc": "C646515",
"mouser": "579-PIC18F26K42I"
},
"distributor_check": {
"checked_at": "2026-10-30T17:05:04Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": "579-PIC18F26K42I",
"status": "found",
"lifecycle": "Obsolete"
}
},
"pins": [
{
"number": "1",
"name": "RE3/MCLR/VPP",
"type": "input",
"description": "Input-only pin: when MCLRE=1 it is the Master Clear input (internal weak pull-up to VDD, noise-filtered reset path), and it is the programming voltage input VPP during programming (Sections 6.5, 16.3.1)."
},
{
"number": "2",
"name": "RA0",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "3",
"name": "RA1",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "4",
"name": "RA2",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "5",
"name": "RA3",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "6",
"name": "RA4",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "7",
"name": "RA5",
"type": "bidirectional",
"description": "PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17)."
},
{
"number": "8",
"name": "VSS",
"type": "power_in",
"description": "Ground reference for the device; all VDD and VSS pins must be connected, and decoupling capacitors are required on each VDD/VSS pair (Sections 2.1, 2.2)."
},
{
"number": "9",
"name": "RA7",
"type": "bidirectional",
"description": "PORTA digital I/O with direction set by TRISA; when an external oscillator is used this pin shares the OSC1/CLKIN oscillator function (Sections 2.5, 7.2)."
},
{
"number": "10",
"name": "RA6",
"type": "bidirectional",
"description": "PORTA digital I/O with direction set by TRISA; when an external oscillator is used this pin shares the OSC2/CLKOUT oscillator function (Sections 2.5, 7.2)."
},
{
"number": "11",
"name": "RC0",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "12",
"name": "RC1",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "13",
"name": "RC2",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "14",
"name": "RC3",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC; this pin also has an I2C-specific pad (RC3I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9)."
},
{
"number": "15",
"name": "RC4",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC; this pin also has an I2C-specific pad (RC4I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9)."
},
{
"number": "16",
"name": "RC5",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "17",
"name": "RC6",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "18",
"name": "RC7",
"type": "bidirectional",
"description": "PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "19",
"name": "VSS",
"type": "power_in",
"description": "Ground reference for the device; all VDD and VSS pins must be connected, and decoupling capacitors are required on each VDD/VSS pair (Sections 2.1, 2.2)."
},
{
"number": "20",
"name": "VDD",
"type": "power_in",
"description": "Positive supply: 1.8V to 3.6V for PIC18LF devices and 2.3V to 5.5V for PIC18F devices; all VDD pins must be decoupled (Sections 1, 2.2)."
},
{
"number": "21",
"name": "RB0",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "22",
"name": "RB1",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB; this pin also has an I2C-specific pad (RB1I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9)."
},
{
"number": "23",
"name": "RB2",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB; this pin also has an I2C-specific pad (RB2I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9)."
},
{
"number": "24",
"name": "RB3",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "25",
"name": "RB4",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "26",
"name": "RB5",
"type": "bidirectional",
"description": "PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2)."
},
{
"number": "27",
"name": "RB6/ICSPCLK",
"type": "bidirectional",
"description": "PORTB digital I/O that serves as the ICSPCLK clock input for in-circuit serial programming and debugging; keep series pull-ups, diodes and capacitors off this pin (Sections 2.4, 16.2)."
},
{
"number": "28",
"name": "RB7/ICSPDAT",
"type": "bidirectional",
"description": "PORTB digital I/O that serves as the ICSPDAT bidirectional serial data pin for in-circuit serial programming and debugging (Sections 2.4, 40)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The page 5 pin diagram text is scrambled. Pin-to-name assignments were reconstructed from the diagra; The diagram labels these pins only as RA7 and RA6. The OSC1/CLKIN and OSC2/CLKOUT mapping is inferre; The diagram gives the name as both RE3/MCLR/VPP and VPP/MCLR/RE3. Pin 1 is taken from the diagram's "
],
"pages_sent": 91,
"cost_usd": 0.4324,
"at": "2026-10-30T17:04:44"
},
"datasheet": {
"url": "https://ww1.microchip.com/downloads/en/DeviceDoc/PIC18(L)F26-27-45-46-47-55-56-57K42-Data-Sheet-40001919G.pdf",
"pages": 841,
"sha256": "dc561c5218c927f3",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 28,
"described": 28,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
},
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"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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"zmin_mm": -0.0,
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"footprint_binding": "identity",
"sha256": "b889a13dbe9ec59e79fa9f1b5118b00bfa54f9582392335ff3365b64afc264b1",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "pic18f26k42-i-etched.step",
"role": "eda",
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"units": "mm",
"origin": "footprint origin = pad-pattern centre",
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"footprint_binding": "identity",
"sha256": "aae401d5425f1a8d5f9371cd4e84c966bf49b736af8f818733b277cc42e0ca22",
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}