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PIC18F26K42-I

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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), SOIC-28-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerpic18f26k42-ifactory-2.0.0extractor-text

Verified PIC18F26K42-I

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 28 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: PIC18F26K42-I · SOIC-28-300mil · 28 pins
  • ✓copper: 28 copper pads, none touching another net
  • ✓datasheet: all 28 pin names found in the 841-page datasheet
  • •distributor (warn): no ['digikey'] number
  • ✓family: SOIC-28W_7.5x17.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-xfj2tq03/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 28 pins = 28 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 28 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ pic18f26k42-i.kicad_sym✓ pic18f26k42-i.kicad_mod✓ pic18f26k42-i.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers pic18f26k42-i: viewers · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
pic18f26k42-i-etched.glb Publish 0.1.0 · Ray 3h ago
pic18f26k42-i-etched.step pic18f26k42-i: factory component page (tier=mfr) · Ray 3h ago
pic18f26k42-i-hero.glb pic18f26k42-i: hero GLB from the etched model (keeps the MPN mark) · Ray 3h ago
pic18f26k42-i-hero.overlay.json Publish 0.1.0 · Ray 3h ago
pic18f26k42-i.glb Publish 0.1.0 · Ray 3h ago
pic18f26k42-i.kicad_mod Publish 0.1.0 · Ray 3h ago
pic18f26k42-i.kicad_sym Publish 0.1.0 · Ray 3h ago
pic18f26k42-i.lbr Publish 0.1.0 · Ray 3h ago
pic18f26k42-i.step Publish 0.1.0 · Ray 3h ago
README.md Publish 0.1.0 · Ray 3h ago
verification.json Verified: Published by the parts factory: tier mfr, 28 pins · Ray 3h ago

PIC18F26K42-I

Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · SOIC-28-300mil

PIC18F26K42-I from Microchip Tech, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RE3/MCLR/VPP input Input-only pin: when MCLRE=1 it is the Master Clear input (internal weak pull-up to VDD, noise-filtered reset path), and it is the programming voltage input VPP during programming (Sections 6.5, 16.3.1).
2 RA0 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
3 RA1 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
4 RA2 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
5 RA3 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
6 RA4 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
7 RA5 bidirectional PORTA digital I/O whose direction is set by TRISA and analog mode by ANSELA; analog functions take priority over digital outputs and peripheral functions are mapped via PPS (Sections 16.1, 16.2, 17).
8 VSS power_in Ground reference for the device; all VDD and VSS pins must be connected, and decoupling capacitors are required on each VDD/VSS pair (Sections 2.1, 2.2).
9 RA7 bidirectional PORTA digital I/O with direction set by TRISA; when an external oscillator is used this pin shares the OSC1/CLKIN oscillator function (Sections 2.5, 7.2).
10 RA6 bidirectional PORTA digital I/O with direction set by TRISA; when an external oscillator is used this pin shares the OSC2/CLKOUT oscillator function (Sections 2.5, 7.2).
11 RC0 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
12 RC1 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
13 RC2 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
14 RC3 bidirectional PORTC digital I/O with direction set by TRISC; this pin also has an I2C-specific pad (RC3I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9).
15 RC4 bidirectional PORTC digital I/O with direction set by TRISC; this pin also has an I2C-specific pad (RC4I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9).
16 RC5 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
17 RC6 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
18 RC7 bidirectional PORTC digital I/O with direction set by TRISC, open-drain control via ODCONC, and peripheral mapping via PPS (Section 16.2).
19 VSS power_in Ground reference for the device; all VDD and VSS pins must be connected, and decoupling capacitors are required on each VDD/VSS pair (Sections 2.1, 2.2).
20 VDD power_in Positive supply: 1.8V to 3.6V for PIC18LF devices and 2.3V to 5.5V for PIC18F devices; all VDD pins must be decoupled (Sections 1, 2.2).
21 RB0 bidirectional PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2).
22 RB1 bidirectional PORTB digital I/O with direction set by TRISB; this pin also has an I2C-specific pad (RB1I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9).
23 RB2 bidirectional PORTB digital I/O with direction set by TRISB; this pin also has an I2C-specific pad (RB2I2C) for I2C/SMBus slew, pull-up and threshold selection (Section 16.2.9).
24 RB3 bidirectional PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2).
25 RB4 bidirectional PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2).
26 RB5 bidirectional PORTB digital I/O with direction set by TRISB, weak pull-up via WPUB, and peripheral mapping via PPS (Section 16.2).
27 RB6/ICSPCLK bidirectional PORTB digital I/O that serves as the ICSPCLK clock input for in-circuit serial programming and debugging; keep series pull-ups, diodes and capacitors off this pin (Sections 2.4, 16.2).
28 RB7/ICSPDAT bidirectional PORTB digital I/O that serves as the ICSPDAT bidirectional serial data pin for in-circuit serial programming and debugging (Sections 2.4, 40).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package SOIC-28-300mil
Category Single Chip Microcomputer/Microcontroller
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD (FOSC ≤ 16 MHz) VDD 2.3 5.5 V FOSC ≤ 16 MHz 741
Supply Voltage VDD (FOSC ≤ 32 MHz) VDD 2.5 5.5 V FOSC ≤ 32 MHz 741
Supply Voltage VDD (FOSC ≤ 64 MHz) VDD 2.7 5.5 V FOSC ≤ 64 MHz 741
RAM Data Retention Voltage VDR 1.7 V Device in Sleep mode 741
VDD Rise Rate to ensure internal Power-on Reset signal SVDD 0.05 V/ms BOR or LPBOR disabled 741
Operating Ambient Temperature Range (Industrial) TA -40 85 °C Industrial temperature range 739
Ambient temperature under bias -40 125 °C 738
Storage temperature -65 150 °C 738
Voltage on VDD pin with respect to VSS -0.3 6.5 V PIC18F26/27/45/46/47/55/56/57K42 (non-LF) 738
Voltage on MCLR pin with respect to VSS -0.3 9 V 738
Voltage on all other pins with respect to VSS -0.3 V Maximum printed as (VDD + 0.3V) 738
Maximum current on VSS pin 350 mA -40°C ≤ TA ≤ +85°C 738
Maximum current on VSS pin 120 mA 85°C ≤ TA ≤ +125°C 738
Maximum current on VDD pin for 28-Pin devices 250 mA -40°C ≤ TA ≤ +85°C 738
Maximum current on VDD pin for 28-Pin devices 85 mA 85°C ≤ TA ≤ +125°C 738
Maximum current on any standard I/O pin 50 mA 738
Clamp current IK 20 mA VPIN < 0 or VPIN > VDD 738
Total power dissipation 800 mW 738
Supply current XT = 4 MHz IDDXT4 680 1100 µA XT = 4 MHz, VDD 3.0V 743
Supply current HFINTOSC = 16 MHz IDDHFO16 3 4.2 mA HFINTOSC = 16 MHz, VDD 3.0V 743
Supply current HFINTOSC = 64 MHz IDDHFOPLL 11.6 14 mA HFINTOSC = 64 MHz, VDD 3.0V 743
Supply current HS+PLL = 64 MHz IDDHSPLL64 9.9 13 mA HS+PLL = 64 MHz, VDD 3.0V 743
Supply current Idle mode IDDIDLE 1.9 2.9 mA Idle mode, HFINTOSC = 16 MHz, VDD 3.0V 743
Power-down current IPD Base, max at +85°C IPD 0.4 4 µA VDD 3.0V 745
Power-down current IPD Base, max at +125°C IPD 0.4 14 µA VDD 3.0V 745
Input Low Voltage, I/O port TTL buffer VIL 0.8 V 4.5V ≤ VDD ≤ 5.5V 746
Input Low Voltage, I/O port SMBus 2.0 VIL 0.8 V 2.7V ≤ VDD ≤ 5.5V 746
Input Low Voltage, I/O port SMBus 3.0 VIL 0.8 V 1.8V ≤ VDD ≤ 5.5V 746
Input High Voltage, I/O port TTL buffer VIH 2 V 4.5V ≤ VDD ≤ 5.5V 746
Input High Voltage, I/O port SMBus 2.0 VIH 2.1 V 2.7V ≤ VDD ≤ 5.5V 746
Input High Voltage, I/O port SMBus 3.0 VIH 1.35 V 1.8V ≤ VDD ≤ 5.5V 746
Input Leakage Current, I/O ports (85°C) IIL -125 5 125 nA VSS ≤ VPIN ≤ VDD, pin at high-impedance, 85°C 746
Input Leakage Current, I/O ports (125°C) IIL -1000 5 1000 nA VSS ≤ VPIN ≤ VDD, pin at high-impedance, 125°C 746
Input Leakage Current, MCLR IIL -200 50 200 nA VSS ≤ VPIN ≤ VDD, pin at high-impedance, 85°C 746
Weak Pull-up Current IPUR 25 120 200 µA VDD = 3.0V, VPIN = VSS 746
Output Low Voltage, I/O ports VOL 0.6 V IOL = 10.0 mA, VDD = 3.0V 746
Pin capacitance, all I/O pins CIO 5 50 pF 746
Byte Erase and Write Cycle Time (Data EEPROM) TD_BEW 4 5 ms 747
Self-Timed Row Erase or Self-Timed Write (Program Flash) TP_REW 2 2.5 ms 747
ECL Clock Frequency FECL 500 kHz 750
ECM Clock Frequency FECM 8 MHz 750
ECH Clock Frequency FECH 64 MHz 750
LP Clock Frequency FLP 100 kHz 750
XT Clock Frequency FXT 4 MHz 750
HS Clock Frequency FHS 20 MHz 750
Secondary Oscillator Clock Frequency FSEC 32.4 32.768 33.1 kHz 750
Internal LFINTOSC Frequency FLFOSC 24.8 31 37.2 kHz 752
PLL Input Frequency Range FPLLIN 4 16 MHz VDD 2.5V 753
PLL Output Frequency Range FPLLOUT 16 64 MHz VDD 2.5V 753
PLL Output Frequency Stability (Jitter) FPLLJIT -0.25 0.25 % VDD 2.5V 753
Port input setup time TIO_SETUP 20 ns 754
Port input hold time TIO_HOLD 50 ns 754
Interrupt-on-Change minimum high or low time TIOC 25 ns 754
Brown-out Reset Voltage BORV = 00 VBOR 2.7 2.85 3 V BORV = 00 756
Brown-out Reset Voltage BORV = 01 VBOR 2.55 2.7 2.85 V BORV = 01 756
Brown-out Reset Voltage BORV = 10 VBOR 2.3 2.45 2.6 V BORV = 10 756
Brown-out Reset Voltage BORV = 11 (PIC18Fxxx) VBOR 2.3 2.45 2.6 V BORV = 11 (PIC18Fxxx) 756
Thermal Resistance Junction to Ambient JA 80 C/W 28-pin SOIC package 748
Thermal Resistance Junction to Case JC 24 C/W 28-pin SOIC package 748
Maximum Junction Temperature TJMAX 150 °C 748

CAD (KiCad official)

  • Symbol: PIC18F26K42-I
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: pic18f26k42-i-etched.step / pic18f26k42-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f26k42-i.step / pic18f26k42-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (841 pp, sha256 dc561c5218c927f3, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF