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PIC18F14K22-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PIC18F14K22-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(4x4)

PIC18F14K22-I from Microchip Tech, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RA3/MCLR/VPP input Input-only pin (Schmitt Trigger) that serves as active-low Master Clear MCLR with internal pull-up or as high-voltage programming input VPP; the RA3 digital input function is only available when MCLR functionality is disabled.
2 RC5/CCP1/P1A bidirectional Digital I/O that also serves as ECCP1 capture input, compare or PWM output CCP1, and Enhanced CCP1 PWM output P1A.
3 RC4/C2OUT/P1B/SRNQ bidirectional Digital I/O that also serves as Comparator 2 output C2OUT, Enhanced CCP1 PWM output P1B, and SR latch inverted output SRNQ.
4 RC3/AN7/C12IN3-/P1C/PGM bidirectional Digital I/O that also serves as ADC channel 7, Comparator C1 and C2 inverting input channel 3, Enhanced CCP1 PWM output P1C, and Low-Voltage ICSP programming enable pin PGM (Schmitt Trigger input, all other functions disabled when enabled by the LVP Configuration bit).
5 RC6/AN8/SS bidirectional Digital I/O that also serves as ADC channel 8 and SPI slave select input SS for the MSSP module (TTL input).
6 RC7/AN9/SDO bidirectional Digital I/O that also serves as ADC channel 9 and SPI data output SDO for the MSSP module.
7 RB7/TX/CK bidirectional Digital I/O with programmable weak pull-up that also serves as EUSART asynchronous transmit TX and synchronous clock CK.
8 RB6/SCK/SCL bidirectional Digital I/O with programmable weak pull-up that also serves as SPI clock SCK and I2C clock SCL for the MSSP module.
9 RB5/AN11/RX/DT bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 11, EUSART asynchronous receive RX, and EUSART synchronous data DT.
10 RB4/AN10/SDI/SDA bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 10, SPI data input SDI, and I2C data SDA for the MSSP module.
11 RC2/AN6/C12IN2-/P1D bidirectional Digital I/O that also serves as ADC channel 6, Comparator C1 and C2 inverting input channel 2, and Enhanced CCP1 PWM output P1D.
12 RC1/AN5/C12IN1- bidirectional Digital I/O that also serves as ADC channel 5 and Comparator C1 and C2 inverting input channel 1.
13 RC0/AN4/C2IN+ bidirectional Digital I/O that also serves as ADC channel 4 and Comparator C2 noninverting input.
14 RA2/AN2/C1OUT/T0CKI/INT2/SRQ bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 2, Comparator C1 output, Timer0 external clock input T0CKI, external interrupt INT2, and SR latch output SRQ.
15 RA1/AN1/C12IN0-/VREF+/INT1/PGC bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 1, Comparator C1 and C2 inverting input channel 0, ADC and DAC reference voltage (high) input VREF+, external interrupt INT1, and ICSP programming clock PGC.
16 RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 0, DAC reference voltage output CVREF/DAC1OUT, ADC and DAC reference voltage (low) input VREF-, Comparator C1 noninverting input, external interrupt INT0, and ICSP programming data PGD.
17 VSS power_in Ground reference for logic and I/O pins.
18 VDD power_in Positive supply for logic and I/O pins.
19 RA5/OSC1/CLKIN/T13CKI bidirectional Digital I/O with programmable weak pull-up that also serves as oscillator crystal input OSC1, external clock source input CLKIN, and Timer1/Timer3 external clock input T13CKI.
20 RA4/AN3/OSC2/CLKOUT bidirectional Digital I/O with programmable weak pull-up that also serves as ADC channel 3, oscillator crystal output OSC2 (crystal modes), and CLKOUT, which outputs the instruction cycle clock at 1/4 the OSC1 frequency in RC mode.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-20-EP(4x4)
Category Embedded Processors & Controllers
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature under bias -40 125 °C 319
Storage temperature -65 150 °C 319
Voltage on VDD pin with respect to VSS (PIC18F1XK22) VDD -0.3 6.5 V PIC18F1XK22 319
Voltage on MCLR pin with respect to VSS -0.3 9 V 319
Voltage on all other pins with respect to VSS -0.3 V Maximum is (VDD + 0.3V) 319
Maximum current on VSS pin 250 mA -40°C ≤ TA ≤ +85°C, Industrial 319
Maximum current on VDD pin 250 mA -40°C ≤ TA ≤ +85°C, Industrial 319
Maximum current sunk by all ports 250 mA 319
Maximum current sourced by all ports 250 mA 319
Maximum output current sunk by any I/O pin 50 mA 319
Maximum output current sourced by any I/O pin 50 mA 319
Clamp current IK 20 mA VPIN < 0 or VPIN > VDD 319
VDD minimum operating supply voltage VDDMIN 2.3 V FOSC ≤ 20 MHz 320
VDD minimum operating supply voltage VDDMIN 3 V FOSC ≤ 64 MHz 320
VDD maximum operating supply voltage VDDMAX 5.5 V 320
Operating ambient temperature, industrial minimum TA_MIN -40 °C Industrial temperature 320
Operating ambient temperature, industrial maximum TA_MAX 85 °C Industrial temperature 320
Supply voltage VDD D001 2.3 5.5 V FOSC ≤ 20 MHz 324
Supply voltage VDD D001 3 5.5 V FOSC ≤ 64 MHz, 85°C 324
RAM data retention voltage VDR 1.7 V Device in Sleep mode 324
VDD rise rate to ensure internal Power-on Reset signal SVDD 0.05 V/ms 324
Power-down base current IPD, +85°C IPD 17 40 µA VDD = 2.3 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Power-down base current IPD, +125°C IPD 55 µA VDD = 2.3 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Power-down base current IPD, +85°C IPD 18 43 µA VDD = 3.0 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Power-down base current IPD, +125°C IPD 65 µA VDD = 3.0 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Power-down base current IPD, +85°C IPD 20 45 µA VDD = 5.0 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Power-down base current IPD, +125°C IPD 80 µA VDD = 5.0 V; WDT, BOR, FVR and T1OSC disabled, all peripherals inactive 332
Primary run supply current IDD (EC medium osc) IDD 0.2 0.32 mA -40°C to +125°C, VDD = 2.3 V, FOSC = 1 MHz, PRI_RUN EC Med Osc 328
Primary run supply current IDD (EC medium osc) IDD 0.27 0.39 mA -40°C to +125°C, VDD = 3.0 V, FOSC = 1 MHz, PRI_RUN EC Med Osc 328
Primary run supply current IDD (EC medium osc) IDD 0.3 0.42 mA -40°C to +125°C, VDD = 5.0 V, FOSC = 1 MHz, PRI_RUN EC Med Osc 328
Primary run supply current IDD (EC high osc) IDD 2.4 3.2 mA -40°C to +125°C, VDD = 2.3 V, FOSC = 16 MHz, PRI_RUN EC High Osc 328
Primary run supply current IDD (EC high osc) IDD 3 4.2 mA -40°C to +125°C, VDD = 3.0 V, FOSC = 16 MHz, PRI_RUN EC High Osc 328
Primary run supply current IDD (EC high osc) IDD 3.3 4.4 mA -40°C to +125°C, VDD = 5.0 V, FOSC = 16 MHz, PRI_RUN EC High Osc 328
Primary run supply current IDD (EC high osc, 64 MHz) IDD 11.5 14 mA -40°C to +125°C, VDD = 3.0 V, FOSC = 64 MHz, PRI_RUN EC High Osc 328
Primary run supply current IDD (EC high osc, 64 MHz) IDD 12.1 14.6 mA -40°C to +125°C, VDD = 5.0 V, FOSC = 64 MHz, PRI_RUN EC High Osc 328
Input low voltage, TTL buffer VIL 0.8 V 4.5 V ≤ VDD ≤ 5.5 V 334
Input high voltage, TTL buffer VIH 2 V 4.5 V ≤ VDD ≤ 5.5 V 334
Input leakage current, I/O ports IIL -5 5 nA VSS ≤ VPIN ≤ VDD, pin at high-impedance, -40°C to 85°C 334
Input leakage current, I/O ports IIL -1000 1000 nA VSS ≤ VPIN ≤ VDD, 85°C to 125°C 334
Input leakage current, MCLR IIL -200 200 nA VSS ≤ VPIN ≤ VDD 334
PORTB weak pull-up current IPUR 50 250 400 µA VDD = 5.0 V, VPIN = VSS 334
Capacitive loading, OSC2 pin COSC2 15 pF XT, HS and LP modes when external clock drives OSC1 336
Capacitive loading, all I/O pins CIO 50 pF 336
HFINTOSC 16 MHz calibrated frequency tolerance HFOSC -2 2 % 0°C ≤ TA ≤ 60°C 342
HFINTOSC 16 MHz calibrated frequency tolerance HFOSC -3 3 % 60°C ≤ TA ≤ +85°C 342
HFINTOSC wake-up from Sleep start-up time TIOSC ST 5 8 µs VDD = 3.0 V, -40°C to +85°C 342
PLL oscillator frequency range FOSC 4 5 MHz VDD = 1.8-3.0 V 342
PLL oscillator frequency range FOSC 4 16 MHz VDD = 3.0-5.0 V, -40°C to +85°C 342
PLL oscillator frequency range FOSC 4 12 MHz VDD = 3.0-5.0 V, 125°C 342
PLL on-chip VCO system frequency FSYS 16 20 MHz VDD = 1.8-3.0 V 342
PLL on-chip VCO system frequency FSYS 16 64 MHz VDD = 3.0-5.0 V, -40°C to +85°C 342
PLL on-chip VCO system frequency FSYS 16 48 MHz VDD = 3.0-5.0 V, 125°C 342
PLL start-up time (lock time) trc 2 ms 342
CLKOUT stability (jitter) CLK -0.25 0.25 % 342
Maximum junction temperature TJMAX 150 °C 338
Thermal resistance junction to ambient JA 43 °C/W 20-pin QFN 4x4mm package 338
Thermal resistance junction to case JC 5.3 °C/W 20-pin QFN 4x4mm package 338

CAD (KiCad official)

  • Symbol: PIC18F14K22-I
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: pic18f14k22-i-etched.step / pic18f14k22-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic18f14k22-i.step / pic18f14k22-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (387 pp, sha256 21f69d409798287f, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF