PIC16F1509-I

{
  "slug": "pic16f1509-i",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), QFN-20-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "pic16f1509-i",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pic16f1509-i.kicad_sym",
    "pic16f1509-i.kicad_mod",
    "pic16f1509-i.glb",
    "pic16f1509-i.step",
    "pic16f1509-i.lbr",
    "docs/hero.png",
    "docs/pic16f1509-i-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pic16f1509-i-hero.glb",
    "pic16f1509-i-hero.overlay.json",
    "pic16f1509-i-etched.glb"
  ],
  "component": {
    "mpn": "PIC16F1509-I",
    "manufacturer": "Microchip Tech",
    "package": "QFN-20-EP(4x4)",
    "pin_count": 21,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589808047469064192",
    "parts": {
      "symbol": "pic16f1509-i.kicad_sym",
      "footprint": "pic16f1509-i.kicad_mod",
      "model_3d": "pic16f1509-i-hero.glb",
      "model_3d_plain": "pic16f1509-i-etched.glb",
      "model_3d_step": "pic16f1509-i-etched.step",
      "model_3d_step_plain": "pic16f1509-i.step",
      "lbr": "pic16f1509-i.lbr"
    },
    "distributor_links": {
      "lcsc": "C637804"
    },
    "distributor_check": {
      "checked_at": "2026-10-20T23:52:25Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "no match"
      },
      "mouser": {
        "pn": null,
        "status": "no match"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "RA3/MCLR/VPP/CLC1IN0/T1G/SS",
        "type": "input",
        "description": "Input-only pin (TRIS always reads 1) that serves as MCLR, an active-low Master Clear with internal pull-up, and as VPP programming voltage (high voltage)."
      },
      {
        "number": "2",
        "name": "RC5",
        "type": "bidirectional",
        "description": "General purpose I/O that can also carry the PWM1 output, the CLC1 output and the CWG1A primary output."
      },
      {
        "number": "3",
        "name": "RC4",
        "type": "bidirectional",
        "description": "General purpose I/O that can also carry the Comparator 2 output C2OUT, the CLC2IN1 input, the CLC4 output and the CWG1B complementary output."
      },
      {
        "number": "4",
        "name": "RC3",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN7, comparator negative inputs C1IN3- and C2IN3-, the PWM2 output and the CLC2IN0 input."
      },
      {
        "number": "5",
        "name": "RC6",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN8, the NCO1 output, the CLC3IN1 input and the SPI slave select input SS."
      },
      {
        "number": "6",
        "name": "RC7/AN9/CLC1IN1/SDO",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN9, the CLC1IN1 input and the SPI data output SDO."
      },
      {
        "number": "7",
        "name": "RB7/CLC3/TX/CK",
        "type": "bidirectional",
        "description": "General purpose I/O that can also carry the CLC3 output and the EUSART asynchronous transmit TX or synchronous clock CK."
      },
      {
        "number": "8",
        "name": "RB6/SCL/SCK",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as the I2C clock SCL (open-drain) and the SPI clock SCK."
      },
      {
        "number": "9",
        "name": "RB5/AN11/CLC4IN0/RX/DT",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN11, the CLC4IN0 input, the EUSART asynchronous receive RX and the synchronous data DT."
      },
      {
        "number": "10",
        "name": "RB4/AN10/CLC3IN0/SDA/SDI",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN10, the CLC3IN0 input, the I2C data SDA (open-drain) and the SPI data input SDI."
      },
      {
        "number": "11",
        "name": "RC2/AN6/C1IN2-/C2IN2-",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN6 and comparator negative inputs C1IN2- and C2IN2-."
      },
      {
        "number": "12",
        "name": "RC1",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN5, comparator negative inputs C1IN1- and C2IN1-, the PWM4 output and the NCO1 output (default pin)."
      },
      {
        "number": "13",
        "name": "RC0/AN4/CLC2/C2IN+",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN4, the CLC2 output and the Comparator 2 positive input C2IN+."
      },
      {
        "number": "14",
        "name": "RA2",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN2, the C1OUT comparator output, the DAC1OUT2 analog output, the Timer0 clock T0CKI, the external interrupt INT, the PWM3 output, the CLC1 output (alternate pin RC5) and the CWG1 fault input CWG1FLT."
      },
      {
        "number": "15",
        "name": "RA1/ICSPCLK",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN1, the ADC positive voltage reference VREF+, the CLC4IN1 input, comparator negative inputs C1IN0- and C2IN0-, and the ICSP programming clock ICSPCLK / in-circuit debug clock ICDCLK."
      },
      {
        "number": "16",
        "name": "RA0/ICSPDAT",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN0, the Comparator 1 positive input C1IN+, the DAC1OUT1 analog output, and the ICSP data ICSPDAT / in-circuit debug data ICDDAT."
      },
      {
        "number": "17",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference for the device; the datasheet recommends the exposed bottom pad also be connected to VSS."
      },
      {
        "number": "18",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin for the device."
      },
      {
        "number": "19",
        "name": "RA5",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as the external clock input CLKIN in EC mode, the Timer1 clock input T1CKI, the NCO1 clock source NCO1CLK, and the secondary oscillator input SOSCI."
      },
      {
        "number": "20",
        "name": "RA4",
        "type": "bidirectional",
        "description": "General purpose I/O that can also serve as ADC channel AN3, the secondary oscillator output SOSCO, the FOSC/4 clock output CLKOUT, and the Timer1 gate input T1G."
      },
      {
        "number": "21",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers are taken from the 20-pin QFN/UQFN column of Table 1 (page 4) and the QFN pin diagram (p; The exposed bottom pad (EP) of the QFN package is drawn in the package outline but is not assigned a; Several pins are multiplexed with alternate functions selected via the APFCON register (SS, T1G, CLC",
          "7/21 pins cited to the wrong page (name found elsewhere): ['14:RA2@p9', '15:RA1/ICSPCLK@p9', '16:RA0/ICSPDAT@p9', '17:VSS@p11']"
        ],
        "pages_sent": 72,
        "cost_usd": 0.2773,
        "at": "2026-10-20T23:49:41"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589808047469064192",
        "pages": 401,
        "sha256": "e20039190e4bde55",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 21,
        "described": 21,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pic16f1509-i.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c9476a1612023de37f27b4972110ab6ac6dc0eaf5ac48957a2e1c497650082a5",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pic16f1509-i-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.0,
          4.0,
          0.77
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3f877b664ebfc19d7b50d80bc0aaf77bd1c0174fa847b7d400ace979efe71e69",
        "checked": "2026-10-20",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}