PIC12F1501-E

{
  "slug": "pic12f1501-e",
  "version": "0.1.0",
  "type": "component",
  "description": "Microchip Tech Microcontrollers (MCU/MPU/SOC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "embedded processors & controllers",
    "pic12f1501-e",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "pic12f1501-e.kicad_sym",
    "pic12f1501-e.kicad_mod",
    "pic12f1501-e.glb",
    "pic12f1501-e.step",
    "pic12f1501-e.lbr",
    "docs/hero.png",
    "docs/pic12f1501-e-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pic12f1501-e-hero.glb",
    "pic12f1501-e-hero.overlay.json",
    "pic12f1501-e-etched.glb"
  ],
  "component": {
    "mpn": "PIC12F1501-E",
    "manufacturer": "Microchip Tech",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Embedded Processors & Controllers",
    "subcategory": "Microcontrollers (MCU/MPU/SOC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588882164535971840",
    "parts": {
      "symbol": "pic12f1501-e.kicad_sym",
      "footprint": "pic12f1501-e.kicad_mod",
      "model_3d": "pic12f1501-e-hero.glb",
      "model_3d_plain": "pic12f1501-e-etched.glb",
      "model_3d_step": "pic12f1501-e-etched.step",
      "model_3d_step_plain": "pic12f1501-e.step",
      "lbr": "pic12f1501-e.lbr"
    },
    "distributor_links": {
      "lcsc": "C80936"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T22:29:04Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply pin; the PIC12F1501 operating voltage range is stated as 2.3V to 5.5V."
      },
      {
        "number": "2",
        "name": "RA5",
        "type": "bidirectional",
        "description": "General purpose I/O (TTL input, CMOS output) that can also serve as the CLKIN external clock input in EC mode, Timer1 clock input (T1CKI), and alternate outputs such as CWG1A, NCO1, CLC2 and PWM4."
      },
      {
        "number": "3",
        "name": "RA4",
        "type": "bidirectional",
        "description": "General purpose I/O (TTL input, CMOS output) that can also serve as ADC channel AN3, comparator C1 negative input, CLKOUT (FOSC/4 output) when enabled, PWM3 output, and Timer1 gate input T1G."
      },
      {
        "number": "4",
        "name": "MCLR/VPP/RA3",
        "type": "input",
        "description": "RA3 is an input-only general purpose pin; when MCLRE is enabled it acts as Master Clear (MCLR) with internal pull-up, and it also carries the high-voltage programming input VPP and the Timer1 gate input T1G."
      },
      {
        "number": "5",
        "name": "RA2",
        "type": "bidirectional",
        "description": "General purpose I/O (Schmitt Trigger input, CMOS output) that can also serve as ADC channel AN2, comparator C1 output, DAC output DACOUT2, Timer0 clock input T0CKI, external interrupt INT, PWM1 output, and CWG Fault input CWG1FLT."
      },
      {
        "number": "6",
        "name": "RA1",
        "type": "bidirectional",
        "description": "General purpose I/O (TTL input, CMOS output) that can also serve as ADC channel AN1, ADC positive reference VREF+, comparator C1 negative input, NCO1 output, and the ICSP programming clock ICSPCLK."
      },
      {
        "number": "7",
        "name": "RA0",
        "type": "bidirectional",
        "description": "General purpose I/O (TTL input, CMOS output) that can also serve as ADC channel AN0, comparator C1 positive input, DAC output DACOUT1, CWG1B output, PWM2 output, and the ICSP data pin ICSPDAT."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference pin for the device."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 4 is multiplexed (RA3 input-only, MCLR, VPP, T1G). Typed as 'input' because RA3 is input-only an; Port pins are typed 'bidirectional' since they are GPIO with peripheral functions; several alternate; The datasheet gives a single 8-pin pinout for PDIP, SOIC, MSOP, DFN and UDFN (page 3 and Table 1 on ",
          "1/8 pins cited to the wrong page (name found elsewhere): ['6:RA1/AN1/VREF+/C1IN0-/NCO1/CLC2IN0/ICSPCLK@p9']"
        ],
        "pages_sent": 59,
        "cost_usd": 0.2054,
        "at": "2026-10-18T22:28:50"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588882164535971840",
        "pages": 292,
        "sha256": "9797df2bbfe0cc6e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pic12f1501-e.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pic12f1501-e-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "ec8c81c1faabfdcc4dc90f7c0ee373d27486fe39455fe0f281813b44838a36eb",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}