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PGA460TPWRQ1

Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-16

PGA460TPWRQ1 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the recommended ground voltage range for GND and GNDP is -0.1 V to 0.1 V.
2 INP input Positive transducer receive input, with a recommended input voltage range of -0.1 V to 0.9 V and an input impedance of 300 kΩ (FSW < 80 kHz).
3 INN input Negative transducer receive input, with a recommended input voltage range of -0.1 V to 0.9 V, and its capacitor should be placed close to the pin.
4 GND power_in Ground pin; the recommended ground voltage range for GND and GNDP is -0.1 V to 0.1 V.
5 OUTA output Transducer driver output A, rated up to 30 V with a sink current limit of 500 mA maximum.
6 GNDP power_in Power ground for the output driver; the recommended ground voltage range is -0.1 V to 0.1 V.
7 OUTB output Transducer driver output B, rated up to 30 V with a sink current limit of 500 mA maximum.
8 IO bidirectional Time command interface data input and output on a high-voltage open-drain pin with an internal 10 kΩ pull-up to VPWR, with recommended range -0.1 V to VPWR.
9 TEST bidirectional Test output pin used to multiplex internal signals, with absolute maximum rating of -0.3 V to 5.5 V and recommended range -0.1 V to VIOREG.
10 TXD output USART interface transmit output at 3.3 V or 5 V CMOS level depending on the configured IOREG voltage, with absolute maximum rating of -0.3 V to 5.5 V.
11 RXD input USART interface receive input at 3.3 V or 5 V CMOS level depending on the configured IOREG voltage, with recommended range -0.1 V to VIOREG and an internal 100 kΩ pull-up.
12 SCLK input USART synchronous mode clock input with recommended range -0.1 V to VIOREG and an internal 100 kΩ pull-down; connect to GND if the synchronous mode is not used.
13 DECPL output Gate (or base) drive output for the external decoupling transistor, driven high at the IOREG level (3.3 V or 5 V) and absolute maximum rating of -0.3 V to 5.5 V.
14 IOREG power_out I/O buffer voltage regulator capacitor pin, regulating to 3.3 V (2.95 V to 3.65 V) or 5 V (4.45 V to 5.65 V); the regulator does not support any external load.
15 VPWR power_in Device supply voltage input, with a recommended range of 6 V to 15 V for transformer topology and 6 V to 28 V for direct-drive topology, and an absolute maximum of 30 V.
16 AVDD power_out Analog voltage regulator capacitor pin, regulating to 1.8 V (1.74 V to 1.9 V) and requiring a 100 nF external capacitor; the regulator does not support any external load.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

CAD (KiCad official)

  • Symbol: PGA460TPWRQ1
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: pga460tpwrq1-etched.step / pga460tpwrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga460tpwrq1.step / pga460tpwrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (116 pp, sha256 b68ce7c2a3a68b62, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF