# PGA460TPW

**Texas Instruments** · ADCs/DACs - Special Purpose · TSSOP-16

PGA460TPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference for transducer signal return and device ground. |
| 2 | INP | input | Positive transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz. |
| 3 | INN | input | Negative transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz. |
| 4 | GND | power_in | Ground reference for device return path. |
| 5 | OUTA | output | Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability. |
| 6 | GNDP | power_in | Power supply ground for output driver stage. |
| 7 | OUTB | output | Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability. |
| 8 | IO | bidirectional | Time-command interface or single-wire UART with open-drain output and 10kΩ internal pull-up to VPWR (0 to VPWR range). |
| 9 | TEST | bidirectional | Test signal output pin for analog/digital signal selection or digital I/O voltage level selection (3.3V or 5V determined at power-on). |
| 10 | TXD | output | USART transmission output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels. |
| 11 | RXD | input | USART reception input at IOREG voltage level with thresholds 0.7×IOREG high and 0.3×IOREG low. |
| 12 | SCLK | input | USART synchronous mode clock input for 8Mbps serial communication (0 to IOREG range). |
| 13 | DECPL | output | Decoupling transistor gate driver output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels. |
| 14 | IOREG | power_in | I/O buffer voltage regulator bypass capacitor pin with 100nF ceramic requirement and selectable output of 3.3V or 5V. |
| 15 | VPWR | power_in | Power supply input voltage (6V to 15V transformer topology, 6V to 28V direct drive, 5V minimum for digital core, absolute maximum 30V). |
| 16 | AVDD | power_in | Analog voltage regulator bypass capacitor pin with 100nF ceramic requirement and regulated output voltage of 1.8V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `PGA460TPW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `pga460tpw-etched.step` / `pga460tpw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pga460tpw.step` / `pga460tpw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/pga460) (116 pp, sha256 `cf8da0778b1e6c64`, retrieved 2026-10-03, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pga460tpw-datasheet.pdf)