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PGA460TPW
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Texas Instruments ADCs/DACs - Special Purpose, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# PGA460TPW++**Texas Instruments** · ADCs/DACs - Special Purpose · TSSOP-16++PGA460TPW from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Ground reference for transducer signal return and device ground. |+| 2 | INP | input | Positive transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz. |+| 3 | INN | input | Negative transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz. |+| 4 | GND | power_in | Ground reference for device return path. |+| 5 | OUTA | output | Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability. |+| 6 | GNDP | power_in | Power supply ground for output driver stage. |+| 7 | OUTB | output | Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability. |+| 8 | IO | bidirectional | Time-command interface or single-wire UART with open-drain output and 10kΩ internal pull-up to VPWR (0 to VPWR range). |+| 9 | TEST | bidirectional | Test signal output pin for analog/digital signal selection or digital I/O voltage level selection (3.3V or 5V determined at power-on). |+| 10 | TXD | output | USART transmission output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels. |+| 11 | RXD | input | USART reception input at IOREG voltage level with thresholds 0.7×IOREG high and 0.3×IOREG low. |+| 12 | SCLK | input | USART synchronous mode clock input for 8Mbps serial communication (0 to IOREG range). |+| 13 | DECPL | output | Decoupling transistor gate driver output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels. |+| 14 | IOREG | power_in | I/O buffer voltage regulator bypass capacitor pin with 100nF ceramic requirement and selectable output of 3.3V or 5V. |+| 15 | VPWR | power_in | Power supply input voltage (6V to 15V transformer topology, 6V to 28V direct drive, 5V minimum for digital core, absolute maximum 30V). |+| 16 | AVDD | power_in | Analog voltage regulator bypass capacitor pin with 100nF ceramic requirement and regulated output voltage of 1.8V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Data Acquisition |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `PGA460TPW`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `pga460tpw-etched.step` / `pga460tpw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pga460tpw.step` / `pga460tpw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/pga460) (116 pp, sha256 `cf8da0778b1e6c64`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pga460tpw-datasheet.pdf)
page.jsonadded+206@@ -0,0 +1,206 @@+{+ "slug": "pga460tpw",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments ADCs/DACs - Special Purpose, TSSOP-16. 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"pga460tpw-etched.step",+ "model_3d_step_plain": "pga460tpw.step",+ "lbr": "pga460tpw.lbr"+ },+ "distributor_links": {+ "lcsc": 1523558,+ "digikey": "296-46921-ND",+ "mouser": "595-PGA460TPW"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T06:47:44Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-46921-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-PGA460TPW",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for transducer signal return and device ground."+ },+ {+ "number": "2",+ "name": "INP",+ "type": "input",+ "description": "Positive transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz."+ },+ {+ "number": "3",+ "name": "INN",+ "type": "input",+ "description": "Negative transducer receive input (0 to 0.9V) with 300kΩ input impedance at frequencies below 80kHz."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for device return path."+ },+ {+ "number": "5",+ "name": "OUTA",+ "type": "output",+ "description": "Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability."+ },+ {+ "number": "6",+ "name": "GNDP",+ "type": "power_in",+ "description": "Power supply ground for output driver stage."+ },+ {+ "number": "7",+ "name": "OUTB",+ "type": "output",+ "description": "Complementary low-side driver output with 30V clamp voltage and 500mA peak current capability."+ },+ {+ "number": "8",+ "name": "IO",+ "type": "bidirectional",+ "description": "Time-command interface or single-wire UART with open-drain output and 10kΩ internal pull-up to VPWR (0 to VPWR range)."+ },+ {+ "number": "9",+ "name": "TEST",+ "type": "bidirectional",+ "description": "Test signal output pin for analog/digital signal selection or digital I/O voltage level selection (3.3V or 5V determined at power-on)."+ },+ {+ "number": "10",+ "name": "TXD",+ "type": "output",+ "description": "USART transmission output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels."+ },+ {+ "number": "11",+ "name": "RXD",+ "type": "input",+ "description": "USART reception input at IOREG voltage level with thresholds 0.7×IOREG high and 0.3×IOREG low."+ },+ {+ "number": "12",+ "name": "SCLK",+ "type": "input",+ "description": "USART synchronous mode clock input for 8Mbps serial communication (0 to IOREG range)."+ },+ {+ "number": "13",+ "name": "DECPL",+ "type": "output",+ "description": "Decoupling transistor gate driver output at IOREG voltage level with 0.2V low and IOREG-0.2V high output levels."+ },+ {+ "number": "14",+ "name": "IOREG",+ "type": "power_in",+ "description": "I/O buffer voltage regulator bypass capacitor pin with 100nF ceramic requirement and selectable output of 3.3V or 5V."+ },+ {+ "number": "15",+ "name": "VPWR",+ "type": "power_in",+ "description": "Power supply input voltage (6V to 15V transformer topology, 6V to 28V direct drive, 5V minimum for digital core, absolute maximum 30V)."+ },+ {+ "number": "16",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog voltage regulator bypass capacitor pin with 100nF ceramic requirement and regulated output voltage of 1.8V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 55,+ "cost_usd": 0.3792,+ "at": "2026-10-03T06:47:16"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/pga460",+ "pages": 116,+ "sha256": "cf8da0778b1e6c64",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}