PGA112AIDGST

{
  "slug": "pga112aidgst",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Programmable/Variable Gain Amplifiers (PGAs/VGAs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "operational amplifier-comparator",
    "pga112aidgst",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "PGA112AIDGST",
    "manufacturer": "Texas Instruments",
    "package": "MSOP-10",
    "pin_count": 10,
    "category": "Operational Amplifier/Comparator",
    "subcategory": "Programmable/Variable Gain Amplifiers (PGAs/VGAs)",
    "datasheet": "https://www.ti.com/lit/ds/symlink/pga112aidgst.pdf",
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      "lbr": "pga112aidgst.lbr"
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    "distributor_links": {
      "lcsc": "C2057508"
    },
    "distributor_check": {
      "checked_at": "2026-10-27T07:28:54Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
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    },
    "pins": [
      {
        "number": "1",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage, 2.2 V to 5.5 V."
      },
      {
        "number": "2",
        "name": "CH1",
        "type": "input",
        "description": "Input MUX channel 1."
      },
      {
        "number": "3",
        "name": "VCAL/CH0",
        "type": "input",
        "description": "Input MUX channel 0 and VCAL input; connect to a low-impedance external reference to use the internal calibration channels (GND, 0.9 VCAL, 0.1 VCAL, VREF), loaded with 100 kΩ typical when CAL2 or CAL3 is selected, otherwise high impedance."
      },
      {
        "number": "4",
        "name": "VREF",
        "type": "power_in",
        "description": "Reference input pin for VOUT offset shift or midsupply; must connect to a low-impedance reference able to source and sink at least 2 mA, or to GND."
      },
      {
        "number": "5",
        "name": "VOUT",
        "type": "output",
        "description": "Analog voltage output; clamped to AVDD + 300 mV when AVDD < DVDD."
      },
      {
        "number": "6",
        "name": "GND",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Clock input for SPI serial interface."
      },
      {
        "number": "8",
        "name": "DIO",
        "type": "bidirectional",
        "description": "Data input/output for SPI serial interface with a weak 10-μA internal pulldown current source."
      },
      {
        "number": "9",
        "name": "CS",
        "type": "input",
        "description": "Chip select line for SPI serial interface."
      },
      {
        "number": "10",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital and op amp output stage supply voltage, 2.2 V to 5.5 V; bypass with a 0.1-μF ceramic capacitor and it must supply digital current and output stage load current."
      }
    ],
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
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        "cost_usd": 0.1006,
        "at": "2026-10-27T07:28:45"
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      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/pga112aidgst.pdf",
        "pages": 62,
        "sha256": "8780e867b7b4f9db",
        "source_tier": "mfr"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 10,
        "described": 10,
        "cites_pages": true,
        "refuses_to_fabricate": true
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}