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PGA112AIDGST

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Texas Instruments Programmable/Variable Gain Amplifiers (PGAs/VGAs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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PGA112AIDGST

Texas Instruments · Programmable/Variable Gain Amplifiers (PGAs/VGAs) · MSOP-10

PGA112AIDGST from Texas Instruments, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply voltage, 2.2 V to 5.5 V.
2 CH1 input Input MUX channel 1.
3 VCAL/CH0 input Input MUX channel 0 and VCAL input; connect to a low-impedance external reference to use the internal calibration channels (GND, 0.9 VCAL, 0.1 VCAL, VREF), loaded with 100 kΩ typical when CAL2 or CAL3 is selected, otherwise high impedance.
4 VREF power_in Reference input pin for VOUT offset shift or midsupply; must connect to a low-impedance reference able to source and sink at least 2 mA, or to GND.
5 VOUT output Analog voltage output; clamped to AVDD + 300 mV when AVDD < DVDD.
6 GND power_in Ground pin.
7 SCLK input Clock input for SPI serial interface.
8 DIO bidirectional Data input/output for SPI serial interface with a weak 10-μA internal pulldown current source.
9 CS input Chip select line for SPI serial interface.
10 DVDD power_in Digital and op amp output stage supply voltage, 2.2 V to 5.5 V; bypass with a 0.1-μF ceramic capacitor and it must supply digital current and output stage load current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package MSOP-10
Category Operational Amplifier/Comparator
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage 7 V 5
Signal input terminals, voltage -0.5 0.5 V GND, 0.5 to AVDD + 0.5 (max is AVDD + 0.5) 5
Signal input terminals, current -10 10 mA 5
Operating temperature (abs max) -40 125 °C 5
Junction temperature 150 °C 5
Storage temperature -65 150 °C 5
Analog supply voltage AVDD 2.2 5 5.5 V 5
Digital supply voltage DVDD 2.2 5 5.5 V 5
Operating temperature -40 25 125 °C 5
Junction-to-ambient thermal resistance RθJA 98.3 °C/W DGS (VSSOP) 10 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 57 °C/W DGS (VSSOP) 10 pins 5
Junction-to-board thermal resistance RθJB 51.2 °C/W DGS (VSSOP) 10 pins 5
Thermal resistance VSSOP-10 θJA 164 °C/W VSSOP-10 8
Input offset voltage VOS -100 25 100 μV AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 2.5 V; typ ±25 6
Input offset voltage VOS -325 75 325 μV AVDD = DVDD = 5 V, VREF = VIN = AVDD/2, VCM = 4.5 V; typ ±75 6
Offset drift -40°C to 125°C dVOS/dT 0.35 1.2 μV/°C AVDD = DVDD = 5 V, VCM = 2.5 V, TA = -40°C to 125°C 6
Offset drift -40°C to 85°C dVOS/dT 0.15 0.9 μV/°C AVDD = DVDD = 5 V, VCM = 2.5 V 6
Offset drift -40°C to 125°C dVOS/dT 0.6 1.8 μV/°C AVDD = DVDD = 5 V, VCM = 4.5 V, TA = -40°C to 125°C 6
Offset drift -40°C to 85°C dVOS/dT 0.3 1.3 μV/°C AVDD = DVDD = 5 V, VCM = 4.5 V 6
Power supply rejection PSRR 5 20 μV/V AVDD = DVDD = 2.2 V to 5.5 V, VCM = 0.5 V, VREF = VIN = AVDD/2 6
Power supply rejection over temperature PSRR 5 40 μV/V Over temperature, TA = -40°C to 125°C 6
Input on-channel current IIN -5 1.5 5 nA VREF = VIN = AVDD/2; typ ±1.5 6
Input voltage range IVR -0.1 0.1 V GND, 0.1 to AVDD + 0.1 (max is AVDD + 0.1) 6
Overvoltage input range -0.3 0.3 V No output phase reversal; GND, 0.3 to AVDD + 0.3 (max is AVDD + 0.3) 6
Channel input capacitance CCH 2 pF 6
Channel switch resistance RSW 150 Ω 6
Amplifier input capacitance CAMP 3 pF 6
Amplifier input resistance RAMP 10 GΩ Input resistance to GND 6
DC gain error G = 1 0.006 0.1 % VOUT = GND + 85 mV to DVDD, 85 mV 6
DC gain error 1 < G ≤ 32 0.1 % VOUT = GND + 85 mV to DVDD, 85 mV 6
DC gain error G ≥ 50 0.3 % VOUT = GND + 85 mV to DVDD, 85 mV 6
DC gain drift G = 1 0.5 ppm/°C VOUT = GND + 85 mV to DVDD, 85 mV, TA = -40°C to 125°C 6
DC gain drift 1 < G ≤ 32 2 ppm/°C VOUT = GND + 85 mV to DVDD, 85 mV, TA = -40°C to 125°C 6
DC gain drift G ≥ 50 6 ppm/°C VOUT = GND + 85 mV to DVDD, 85 mV, TA = -40°C to 125°C 6
CAL2 DC gain error 0.02 % Op Amp + Input = 0.9 VCAL, VREF = VCAL = AVDD/2, G = 1 6
CAL3 DC gain error 0.02 % Op Amp + Input = 0.1 VCAL, VREF = VCAL = AVDD/2, G = 1 6
Input off-channel current ILKG -1 0.05 1 nA VREF = GND, VOFF-CHANNEL = AVDD/2, VON-CHANNEL = AVDD/2, 0.1 V; typ ±0.05 7
Output swing from rail, ±0.25 mA 0.05 0.05 V IOUT = ±0.25 mA, AVDD ≥ DVDD; GND + 0.05 to DVDD, 0.05 7
Output swing from rail, ±5 mA 0.25 0.25 V IOUT = ±5 mA, AVDD ≥ DVDD; GND + 0.25 to DVDD, 0.25 7
Short circuit current ISC -30 60 mA -30/+60 7
Operating voltage range AVDD AVDD 2.2 5.5 V 7
Operating voltage range DVDD DVDD 2.2 5.5 V 7
Quiescent current analog IQA 0.33 0.45 mA IO = 0, G = 1, VOUT = VREF 7
Quiescent current analog over temperature IQA 0.45 mA TA = -40°C to 125°C 7
Quiescent current digital IQD 0.75 1.2 mA IO = 0, G = 1, VOUT = VREF, SCLK at 10 MHz, CS = Logic 0, DIO or DIN = Logic 0 7
Quiescent current digital over temperature IQD 1.2 mA TA = -40°C to 125°C 7
Shutdown current analog + digital ISDA + ISDD 4 μA IO = 0, VOUT = VREF, G = 1, SCLK Idle 7
POR trip voltage 1.6 V DVDD < POR Trip Voltage 7
Specified temperature range -40 125 °C 8
Digital input logic low 0 0.3 V 0 to 0.3DVDD (max is 0.3DVDD) 8
Input leakage current (SCLK and CS only) -1 1 μA 8
Digital input logic high 0.7 1 V 0.7DVDD to DVDD (min is 0.7DVDD, max is DVDD) 8
Digital output logic high -0.4 0 V IOH = -3 mA (sourcing); DVDD, 0.4 to DVDD (offsets from DVDD) 8
Digital output logic low 0 0.4 V IOL = 3 mA (sinking); GND to GND + 0.4 (offset from GND) 8
Enable time 4 μs 8
SCLK frequency fSCLK 10 MHz 9

CAD (KiCad official)

  • Symbol: PGA112AIDGST
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: pga112aidgst-etched.step / pga112aidgst-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pga112aidgst.step / pga112aidgst.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (62 pp, sha256 8780e867b7b4f9db, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF