# PDTC114YU

**Nexperia** · Digital Transistors · SOT-323

PDTC114YU from Nexperia, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I | input | Input (base). Connects through the internal R1 = 10 kΩ series bias resistor to the base of the NPN transistor, with internal R2 = 47 kΩ shunt to GND. Off-state input voltage max 0.5 V; on-state input voltage min 1.4 V. Absolute max input voltage range -6 V to +40 V. |
| 2 | GND | passive | Ground (emitter). Emitter of the internal NPN transistor and the return leg of the R2 bias resistor; tie to circuit ground/common. |
| 3 | O | output | Output (collector) of the internal NPN transistor. Open-collector switching output rated 50 V VCEO / 100 mA IO, VCEsat ≤ 100 mV at IC = 5 mA, IB = 0.25 mA. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Ordering variants

Same part, different packaging or reel option.

- `PDTC114YU`

## CAD (KiCad official)

- Symbol: `PDTC114YU`
- Footprint: `Package_TO_SOT_SMD:SOT-323_SC-70`
- 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files: `pdtc114yu-etched.step` / `pdtc114yu-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pdtc114yu.step` / `pdtc114yu.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/PDTC114YU.pdf) (10 pp, sha256 `009c88eea79d14d0`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/pdtc114yu-datasheet.pdf)