component
PDTB114ETR
Public Made by Adomby adom
Nexperia Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPDTB114ETR
Nexperia · Digital Transistors · SOT-23
PDTB114ETR from Nexperia, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | input (base) | input | Input (base) of the built-in transistor, which is driven through bias resistor R1 (10 kΩ typ. for PDTB114ET); input voltage is limited to -50 V to +10 V per the limiting values. |
| 2 | GND (emitter) | power_in | Ground connection at the emitter of the built-in PNP transistor, with R2 (10 kΩ) connected between base and emitter. |
| 3 | output (collector) | output | Output (collector) of the built-in PNP transistor, rated for 500 mA output current and 50 V collector-emitter voltage (open base). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| collector-base voltage | VCBO | 50 | V | open emitter | 3 | ||
| collector-emitter voltage | VCEO | 50 | V | open base | 3 | ||
| emitter-base voltage | VEBO | 10 | V | open collector; PDTB114ET | 3 | ||
| input voltage | VI | -50 | 10 | V | PDTB114ET | 3 | |
| output current | IO | 500 | mA | 3 | |||
| total power dissipation | Ptot | 320 | mW | Tamb ≤ 25 °C; FR4 PCB, single-sided copper, standard footprint [1] | 3 | ||
| total power dissipation | Ptot | 460 | mW | Tamb ≤ 25 °C; FR4 PCB, 4-layer copper, standard footprint [2] | 3 | ||
| junction temperature | Tj | 175 | °C | 3 | |||
| ambient temperature | Tamb | -55 | 175 | °C | 3 | ||
| storage temperature | Tstg | -55 | 175 | °C | 3 | ||
| thermal resistance from junction to ambient | Rth(j-a) | 470 | K/W | in free air; FR4 PCB, single-sided copper, standard footprint [1] | 4 | ||
| thermal resistance from junction to ambient | Rth(j-a) | 327 | K/W | in free air; FR4 PCB, 4-layer copper, standard footprint [2] | 4 | ||
| collector-base cut-off current | ICBO | 100 | nA | VCB = 40 V; IE = 0 A | 6 | ||
| collector-emitter cut-off current | ICEO | 0.5 | A | VCE = 50 V; IB = 0 A | 6 | ||
| emitter-base cut-off current | IEBO | 0.4 | mA | VEB = 5 V; IC = 0 A; PDTB114ET | 6 | ||
| DC current gain | hFE | 70 | VCE = 5 V; IC = 50 mA; PDTB114ET | 6 | |||
| collector-emitter saturation voltage | VCEsat | 100 | mV | IC = 50 mA; IB = 2.5 mA | 6 | ||
| off-state input voltage | VI(off) | 0.6 | 1 | 1.5 | V | VCE = 5 V; IC = 100 A; PDTB114ET | 6 |
| on-state input voltage | VI(on) | 1 | 2.2 | 3 | V | VCE = 0.3 V; IC = 20 mA; PDTB114ET | 6 |
| bias resistor 1 (input) | R1 | 7 | 10 | 13 | k | PDTB114ET | 6 |
| bias resistor ratio R2/R1 | R2/R1 | 0.9 | 1 | 1.1 | PDTB114ET | 6 |
CAD (KiCad official)
- Symbol:
PDTB114ETR - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
pdtb114etr-etched.step/pdtb114etr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pdtb114etr.step/pdtb114etr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (18 pp, sha256
f04378662d3b464e, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).