PCI9052G

{
  "slug": "pci9052g",
  "version": "0.1.0",
  "type": "component",
  "description": "Broadcom Limited Interface - Specialized, PQFP-160(28x28). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "interface",
    "pci9052g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
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    "pci9052g.kicad_mod",
    "pci9052g.glb",
    "pci9052g.step",
    "pci9052g.lbr",
    "docs/hero.png",
    "docs/pci9052g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pci9052g-hero.glb",
    "pci9052g-hero.overlay.json",
    "pci9052g-etched.glb"
  ],
  "component": {
    "mpn": "PCI9052G",
    "manufacturer": "Broadcom Limited",
    "package": "PQFP-160(28x28)",
    "pin_count": 160,
    "category": "Interface",
    "subcategory": "Interface - Specialized",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181595128598528",
    "parts": {
      "symbol": "pci9052g.kicad_sym",
      "footprint": "pci9052g.kicad_mod",
      "model_3d": "pci9052g-hero.glb",
      "model_3d_plain": "pci9052g-etched.glb",
      "model_3d_step": "pci9052g-etched.step",
      "model_3d_step_plain": "pci9052g.step",
      "lbr": "pci9052g.lbr"
    },
    "distributor_links": {
      "lcsc": "C14636",
      "digikey": "516-3365-ND",
      "mouser": "862-PCI9052-G"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T02:01:14Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "516-3365-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "862-PCI9052-G",
        "status": "found",
        "lifecycle": "Obsolete"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "2",
        "name": "AD23",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 23 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "3",
        "name": "AD22",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 22 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "4",
        "name": "AD21",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 21 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "5",
        "name": "AD20",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 20 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "6",
        "name": "AD19",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 19 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "7",
        "name": "AD18",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 18 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "8",
        "name": "AD17",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 17 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "9",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "10",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "11",
        "name": "AD16",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 16 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "12",
        "name": "C/BE2#",
        "type": "input",
        "description": "PCI bus command during address phase and byte enable 2 during data phase."
      },
      {
        "number": "13",
        "name": "FRAME#",
        "type": "input",
        "description": "Driven by the current master to indicate the beginning and duration of an access; de-asserted in the final data phase."
      },
      {
        "number": "14",
        "name": "IRDY#",
        "type": "input",
        "description": "Initiator ready, indicating the bus master's ability to complete the current data phase."
      },
      {
        "number": "15",
        "name": "TRDY#",
        "type": "tri_state",
        "description": "Target ready, indicating the target's ability to complete the current data phase (sustained tri-state)."
      },
      {
        "number": "16",
        "name": "DEVSEL#",
        "type": "tri_state",
        "description": "Device select, driven when the device has decoded its address as the current access target (sustained tri-state)."
      },
      {
        "number": "17",
        "name": "STOP#",
        "type": "tri_state",
        "description": "Indicates the current target is requesting the master to stop the current transaction (sustained tri-state)."
      },
      {
        "number": "18",
        "name": "LOCK#",
        "type": "input",
        "description": "Indicates an atomic operation that may require multiple transactions to complete."
      },
      {
        "number": "19",
        "name": "PERR#",
        "type": "tri_state",
        "description": "Reports data parity errors during all PCI transactions except a Special cycle (sustained tri-state)."
      },
      {
        "number": "20",
        "name": "SERR#",
        "type": "output",
        "description": "Reports address parity errors, data parity errors on Special Cycle, or other catastrophic system errors (open drain)."
      },
      {
        "number": "21",
        "name": "PAR",
        "type": "bidirectional",
        "description": "Even parity across AD[31:0] and C/BE[3:0]#, stable one clock after the address phase and valid per the PCI data phase timing."
      },
      {
        "number": "22",
        "name": "C/BE1#",
        "type": "input",
        "description": "PCI bus command during address phase and byte enable 1 during data phase."
      },
      {
        "number": "23",
        "name": "AD15",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 15 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "24",
        "name": "AD14",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 14 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "25",
        "name": "AD13",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 13 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "26",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "27",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "28",
        "name": "AD12",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 12 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "29",
        "name": "AD11",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 11 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "30",
        "name": "AD10",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 10 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "31",
        "name": "AD9",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 9 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "32",
        "name": "AD8",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 8 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "33",
        "name": "C/BE0#",
        "type": "input",
        "description": "PCI bus command during address phase and byte enable 0 during data phase."
      },
      {
        "number": "34",
        "name": "AD7",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 7 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "35",
        "name": "AD6",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 6 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "36",
        "name": "AD5",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 5 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "37",
        "name": "AD4",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 4 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "38",
        "name": "AD3",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 3 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "39",
        "name": "AD2",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 2 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "40",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "41",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "42",
        "name": "AD1",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 1 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "43",
        "name": "AD0",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 0 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "44",
        "name": "INTA#",
        "type": "output",
        "description": "PCI interrupt A request output (open drain)."
      },
      {
        "number": "45",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect in Non-Multiplexed and Multiplexed modes; in ISA Interface mode this pin is CHRDY input and should be pulled high."
      },
      {
        "number": "46",
        "name": "LBE3#",
        "type": "tri_state",
        "description": "Local byte enable 3 (LAD[31:24] in 32-bit bus; BHE#/LAD[15:8] in 16-bit bus); in ISA mode it is SBHE# for Local Address Spaces 0 and 1."
      },
      {
        "number": "47",
        "name": "LBE2#",
        "type": "tri_state",
        "description": "Local byte enable 2 (LAD[23:16] in 32-bit bus); not used in 16-bit or 8-bit bus modes."
      },
      {
        "number": "48",
        "name": "LBE1#",
        "type": "tri_state",
        "description": "Local byte enable 1 (LAD[15:8] in 32-bit bus; LA1 in 16-bit and 8-bit bus modes); in ISA mode it is ISAA1."
      },
      {
        "number": "49",
        "name": "LBE0#",
        "type": "tri_state",
        "description": "Local byte enable 0 (LAD[7:0]; BLE# in 16-bit bus, LA0 in 8-bit bus); in ISA mode it is ISAA0."
      },
      {
        "number": "50",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "51",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "52",
        "name": "LAD31",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 31 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "53",
        "name": "LAD30",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 30 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "54",
        "name": "LAD29",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 29 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "55",
        "name": "LAD28",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 28 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "56",
        "name": "LAD27",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 27 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "57",
        "name": "LAD26",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 26 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "58",
        "name": "LAD25",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 25 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "59",
        "name": "LAD24",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 24 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "60",
        "name": "LAD23",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 23 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "61",
        "name": "LAD22",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 22 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "62",
        "name": "LAD21",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 21 (32-bit bus width); carries data during the data phase."
      },
      {
        "number": "63",
        "name": "BCLKO",
        "type": "output",
        "description": "Buffered version of the PCI clock for optional Local Bus use (24 mA totem pole); not in phase with the PCI clock."
      },
      {
        "number": "64",
        "name": "ALE",
        "type": "tri_state",
        "description": "Address latch enable, asserted during the address phase and de-asserted before the data phase; pulse width depends on LCLK frequency (BALE in ISA mode for spaces 0 and 1)."
      },
      {
        "number": "65",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "66",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "67",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect in Non-Multiplexed and Multiplexed modes; in ISA Interface mode this pin is NOWS# input, held high by an internal 80 kΩ pull-up and can be tied high or left open otherwise."
      },
      {
        "number": "68",
        "name": "MODE",
        "type": "input",
        "description": "Bus mode select: 0 = Non-Multiplexed mode, 1 = Multiplexed mode; must be 0 for ISA Interface mode."
      },
      {
        "number": "69",
        "name": "LAD20",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 20 (16/32-bit bus width); carries data during the data phase."
      },
      {
        "number": "70",
        "name": "LAD19",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 19 (16/32-bit bus width); carries data during the data phase."
      },
      {
        "number": "71",
        "name": "LAD18",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 18 (16/32-bit bus width); carries data during the data phase."
      },
      {
        "number": "72",
        "name": "LAD17",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 17 (16/32-bit bus width); carries data during the data phase."
      },
      {
        "number": "73",
        "name": "LAD16",
        "type": "bidirectional",
        "description": "Local multiplexed data bus bit 16 (16/32-bit bus width); carries data during the data phase."
      },
      {
        "number": "74",
        "name": "LAD15",
        "type": "bidirectional",
        "description": "Local data bus bit 15 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "75",
        "name": "LAD14",
        "type": "bidirectional",
        "description": "Local data bus bit 14 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "76",
        "name": "LAD13",
        "type": "bidirectional",
        "description": "Local data bus bit 13 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "77",
        "name": "LAD12",
        "type": "bidirectional",
        "description": "Local data bus bit 12 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "78",
        "name": "LAD11",
        "type": "bidirectional",
        "description": "Local data bus bit 11 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "79",
        "name": "LAD10",
        "type": "bidirectional",
        "description": "Local data bus bit 10 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "80",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "81",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "82",
        "name": "LAD9",
        "type": "bidirectional",
        "description": "Local data bus bit 9 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "83",
        "name": "LAD8",
        "type": "bidirectional",
        "description": "Local data bus bit 8 (16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "84",
        "name": "LAD7",
        "type": "bidirectional",
        "description": "Local data bus bit 7 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "85",
        "name": "LAD6",
        "type": "bidirectional",
        "description": "Local data bus bit 6 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "86",
        "name": "LAD5",
        "type": "bidirectional",
        "description": "Local data bus bit 5 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "87",
        "name": "LAD4",
        "type": "bidirectional",
        "description": "Local data bus bit 4 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "88",
        "name": "LAD3",
        "type": "bidirectional",
        "description": "Local data bus bit 3 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "89",
        "name": "LAD2",
        "type": "bidirectional",
        "description": "Local data bus bit 2 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "90",
        "name": "LAD1",
        "type": "bidirectional",
        "description": "Local data bus bit 1 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "91",
        "name": "LAD0",
        "type": "bidirectional",
        "description": "Local data bus bit 0 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase."
      },
      {
        "number": "92",
        "name": "LA2",
        "type": "tri_state",
        "description": "Local address bus bit 2 (upper 26 bits of the 28-bit physical address, LA[27:2]); increments during bursts."
      },
      {
        "number": "93",
        "name": "LA3",
        "type": "tri_state",
        "description": "Local address bus bit 3 (LA[27:2]); increments during bursts."
      },
      {
        "number": "94",
        "name": "LA4",
        "type": "tri_state",
        "description": "Local address bus bit 4 (LA[27:2]); increments during bursts."
      },
      {
        "number": "95",
        "name": "LA5",
        "type": "tri_state",
        "description": "Local address bus bit 5 (LA[27:2]); increments during bursts."
      },
      {
        "number": "96",
        "name": "LA6",
        "type": "tri_state",
        "description": "Local address bus bit 6 (LA[27:2]); increments during bursts."
      },
      {
        "number": "97",
        "name": "LA7",
        "type": "tri_state",
        "description": "Local address bus bit 7 (LA[27:2]); increments during bursts."
      },
      {
        "number": "98",
        "name": "LA8",
        "type": "tri_state",
        "description": "Local address bus bit 8 (LA[27:2]); increments during bursts."
      },
      {
        "number": "99",
        "name": "TEST",
        "type": "input",
        "description": "Test pin: tie low for normal operation; pulling high places all outputs except RD# in high impedance."
      },
      {
        "number": "100",
        "name": "LA9",
        "type": "tri_state",
        "description": "Local address bus bit 9 (LA[27:2]); increments during bursts."
      },
      {
        "number": "101",
        "name": "LA10",
        "type": "tri_state",
        "description": "Local address bus bit 10 (LA[27:2]); increments during bursts."
      },
      {
        "number": "102",
        "name": "LA11",
        "type": "tri_state",
        "description": "Local address bus bit 11 (LA[27:2]); increments during bursts."
      },
      {
        "number": "103",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "104",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "105",
        "name": "LA12",
        "type": "tri_state",
        "description": "Local address bus bit 12 (LA[27:2]); increments during bursts."
      },
      {
        "number": "106",
        "name": "LA13",
        "type": "tri_state",
        "description": "Local address bus bit 13 (LA[27:2]); increments during bursts."
      },
      {
        "number": "107",
        "name": "LA14",
        "type": "tri_state",
        "description": "Local address bus bit 14 (LA[27:2]); increments during bursts."
      },
      {
        "number": "108",
        "name": "LA15",
        "type": "tri_state",
        "description": "Local address bus bit 15 (LA[27:2]); increments during bursts."
      },
      {
        "number": "109",
        "name": "LA16",
        "type": "tri_state",
        "description": "Local address bus bit 16 (LA[27:2]); increments during bursts."
      },
      {
        "number": "110",
        "name": "LA17",
        "type": "tri_state",
        "description": "Local address bus bit 17 (LA[27:2]); increments during bursts."
      },
      {
        "number": "111",
        "name": "LA18",
        "type": "tri_state",
        "description": "Local address bus bit 18 (LA[27:2]); increments during bursts."
      },
      {
        "number": "112",
        "name": "LA19",
        "type": "tri_state",
        "description": "Local address bus bit 19 (LA[27:2]); increments during bursts."
      },
      {
        "number": "113",
        "name": "LA20",
        "type": "tri_state",
        "description": "Local address bus bit 20 (LA[27:2]); increments during bursts."
      },
      {
        "number": "114",
        "name": "LA21",
        "type": "tri_state",
        "description": "Local address bus bit 21 (LA[27:2]); increments during bursts."
      },
      {
        "number": "115",
        "name": "LA22",
        "type": "tri_state",
        "description": "Local address bus bit 22 (LA[27:2]); increments during bursts."
      },
      {
        "number": "116",
        "name": "LA23",
        "type": "tri_state",
        "description": "Local address bus bit 23 (LA[27:2]); increments during bursts."
      },
      {
        "number": "117",
        "name": "LA24",
        "type": "tri_state",
        "description": "Local address bus bit 24 (LA[27:2]); increments during bursts."
      },
      {
        "number": "118",
        "name": "LA25",
        "type": "tri_state",
        "description": "Local address bus bit 25 (LA[27:2]); increments during bursts."
      },
      {
        "number": "119",
        "name": "LA26",
        "type": "tri_state",
        "description": "Local address bus bit 26 (LA[27:2]); increments during bursts."
      },
      {
        "number": "120",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "121",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "122",
        "name": "LA27",
        "type": "tri_state",
        "description": "Local address bus bit 27, the most significant bit of the 28-bit physical address (LA[27:2])."
      },
      {
        "number": "123",
        "name": "ADS#",
        "type": "tri_state",
        "description": "Address strobe, asserted for the first clock of a local bus access to indicate a valid address (12 mA)."
      },
      {
        "number": "124",
        "name": "BLAST#",
        "type": "tri_state",
        "description": "Burst last, driven by the local bus master to indicate the last transfer; not asserted until internal wait states expire."
      },
      {
        "number": "125",
        "name": "WR#",
        "type": "tri_state",
        "description": "General purpose write strobe, timing controlled by the current Bus Region Descriptor register (12 mA)."
      },
      {
        "number": "126",
        "name": "RD#",
        "type": "tri_state",
        "description": "General purpose read strobe, timing controlled by the current Bus Region Descriptor; provides NAND tree output when TEST is high (12 mA)."
      },
      {
        "number": "127",
        "name": "LW/R#",
        "type": "tri_state",
        "description": "Local write/read indicator, asserted low for reads and high for writes."
      },
      {
        "number": "128",
        "name": "LRDYi#",
        "type": "input",
        "description": "Local ready input indicating read data is on the local bus or write data is accepted; sampled only after internal wait states expire; internal 80 kΩ pull-up."
      },
      {
        "number": "129",
        "name": "BTERM#",
        "type": "input",
        "description": "Burst terminate ready input that breaks a burst and forces a new address cycle when enabled; internal 80 kΩ pull-up."
      },
      {
        "number": "130",
        "name": "CS0#",
        "type": "tri_state",
        "description": "General purpose chip select 0 with programmable base and range; redefined as MEMRD# in ISA Interface mode (8 mA)."
      },
      {
        "number": "131",
        "name": "CS1#",
        "type": "tri_state",
        "description": "General purpose chip select 1 with programmable base and range; redefined as MEMWR# in ISA Interface mode (8 mA)."
      },
      {
        "number": "132",
        "name": "LRESET#",
        "type": "output",
        "description": "Local reset output asserted when the PCI 9052 is reset; inverted to LRESET (active high) in ISA Interface mode (8 mA totem pole)."
      },
      {
        "number": "133",
        "name": "LHOLDA",
        "type": "output",
        "description": "Hold acknowledge asserted to grant local bus control to a local bus master; de-asserted to preempt when the PCI 9052 needs the bus (8 mA totem pole)."
      },
      {
        "number": "134",
        "name": "LHOLD",
        "type": "input",
        "description": "Hold request from a local bus master; pull or drive low to make the PCI 9052 local bus master (no internal pull resistor)."
      },
      {
        "number": "135",
        "name": "LCLK",
        "type": "input",
        "description": "Local clock input, required, up to 40 MHz, may be asynchronous to the PCI clock."
      },
      {
        "number": "136",
        "name": "LINTi2",
        "type": "input",
        "description": "Local interrupt 2 input, programmable active-low or active-high level-sensitive (or edge-triggered) interrupt that can assert INTA#."
      },
      {
        "number": "137",
        "name": "LINTi1",
        "type": "input",
        "description": "Local interrupt 1 input, programmable active-low or active-high level-sensitive (or edge-triggered) interrupt that can assert INTA#."
      },
      {
        "number": "138",
        "name": "USER0/WAITO#",
        "type": "bidirectional",
        "description": "Configurable user I/O 0 or WAIT output (WAITO#); default is USER0 input, redefined as IORD# in ISA Interface mode (8 mA)."
      },
      {
        "number": "139",
        "name": "USER1/LLOCKo#",
        "type": "bidirectional",
        "description": "Configurable user I/O 1 or LLOCK output (LLOCKo#); default is USER1 input, redefined as IOWR# in ISA Interface mode (8 mA)."
      },
      {
        "number": "140",
        "name": "USER2/CS2#",
        "type": "bidirectional",
        "description": "Configurable user I/O 2 or chip select 2 output (CS2#); default is USER2 input (8 mA)."
      },
      {
        "number": "141",
        "name": "USER3/CS3#",
        "type": "bidirectional",
        "description": "Configurable user I/O 3 or chip select 3 output (CS3#); default is USER3 input (8 mA)."
      },
      {
        "number": "142",
        "name": "EECS",
        "type": "output",
        "description": "Serial EEPROM chip select output (8 mA totem pole)."
      },
      {
        "number": "143",
        "name": "EEDO",
        "type": "input",
        "description": "Serial EEPROM data out (read data from EEPROM); requires an external pull-up if no or a blank EEPROM is used."
      },
      {
        "number": "144",
        "name": "EESK",
        "type": "output",
        "description": "Serial EEPROM clock output (8 mA totem pole)."
      },
      {
        "number": "145",
        "name": "EEDI",
        "type": "output",
        "description": "Serial EEPROM data in (write data to EEPROM) output (8 mA totem pole)."
      },
      {
        "number": "146",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052."
      },
      {
        "number": "147",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "148",
        "name": "RST#",
        "type": "input",
        "description": "PCI reset input that brings PCI-specific registers, sequencers and signals to a consistent state."
      },
      {
        "number": "149",
        "name": "CLK",
        "type": "input",
        "description": "PCI clock providing timing for all PCI transactions; operates up to 33 MHz."
      },
      {
        "number": "150",
        "name": "AD31",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 31 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "151",
        "name": "AD30",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 30 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "152",
        "name": "AD29",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 29 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "153",
        "name": "AD28",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 28 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "154",
        "name": "AD27",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 27 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "155",
        "name": "AD26",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 26 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "156",
        "name": "AD25",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 25 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "157",
        "name": "AD24",
        "type": "bidirectional",
        "description": "PCI multiplexed address/data bit 24 (AD[31:0] bus, address phase then data phases)."
      },
      {
        "number": "158",
        "name": "C/BE3#",
        "type": "input",
        "description": "PCI bus command during address phase and byte enable 3 during data phase."
      },
      {
        "number": "159",
        "name": "IDSEL",
        "type": "input",
        "description": "Initialization device select, used as chip select during PCI configuration read or write transactions."
      },
      {
        "number": "160",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin names are given in Non-Multiplexed mode (MODE=0), the default and ISA-compatible mode. Several p; Power pins are printed as type 'I' in Table 9-5. They are mapped here to KiCad power_in (VDD as supp; Per-bit numbering for AD[31:0], LA[27:2] and LAD[31:0] is inferred from the pin ranges in Tables 9-7",
          "89/160 pins cited to the wrong page (name found elsewhere): ['2:AD23@p139', '3:AD22@p139', '4:AD21@p139', '5:AD20@p139']"
        ],
        "pages_sent": 38,
        "cost_usd": 0.3392,
        "at": "2026-10-21T01:58:32"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181595128598528",
        "pages": 160,
        "sha256": "aced364bc8bfdc5b",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 160,
        "described": 160,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "pci9052g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          31.25,
          31.25,
          1.6
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "fd4c6316024c982298de124fc0983ff573d5c8b7292b2381955006a86031c878",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "pci9052g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          31.25,
          31.25,
          1.6
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "db6bb543734be69657c86f8bec7cccda358aa87aa198a47158832609c1d826cf",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}