component

PCI9052G

Public Made by Adom

by adom

Broadcom Limited Interface - Specialized, PQFP-160(28x28). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacepci9052gfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 13d ago
viewers pci9052g: viewers · Ray 13d ago
package.json Publish 0.1.0 · Ray 13d ago
page.json Set visibility: public · Ray 13d ago
pci9052g-etched.glb Publish 0.1.0 · Ray 13d ago
pci9052g-etched.step pci9052g: factory component page (tier=lcsc) · Ray 13d ago
pci9052g-hero.glb pci9052g: hero GLB from the etched model (keeps the MPN mark) · Ray 13d ago
pci9052g-hero.overlay.json Publish 0.1.0 · Ray 13d ago
pci9052g.glb Publish 0.1.0 · Ray 13d ago
pci9052g.kicad_mod Publish 0.1.0 · Ray 13d ago
pci9052g.kicad_sym Publish 0.1.0 · Ray 13d ago
pci9052g.lbr Publish 0.1.0 · Ray 13d ago
pci9052g.step Publish 0.1.0 · Ray 13d ago
README.md Publish 0.1.0 · Ray 13d ago

PCI9052G

Broadcom Limited · Interface - Specialized · PQFP-160(28x28)

PCI9052G from Broadcom Limited, in a PQFP-160(28x28). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
2 AD23 bidirectional PCI multiplexed address/data bit 23 (AD[31:0] bus, address phase then data phases).
3 AD22 bidirectional PCI multiplexed address/data bit 22 (AD[31:0] bus, address phase then data phases).
4 AD21 bidirectional PCI multiplexed address/data bit 21 (AD[31:0] bus, address phase then data phases).
5 AD20 bidirectional PCI multiplexed address/data bit 20 (AD[31:0] bus, address phase then data phases).
6 AD19 bidirectional PCI multiplexed address/data bit 19 (AD[31:0] bus, address phase then data phases).
7 AD18 bidirectional PCI multiplexed address/data bit 18 (AD[31:0] bus, address phase then data phases).
8 AD17 bidirectional PCI multiplexed address/data bit 17 (AD[31:0] bus, address phase then data phases).
9 VSS power_in Ground pin.
10 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
11 AD16 bidirectional PCI multiplexed address/data bit 16 (AD[31:0] bus, address phase then data phases).
12 C/BE2# input PCI bus command during address phase and byte enable 2 during data phase.
13 FRAME# input Driven by the current master to indicate the beginning and duration of an access; de-asserted in the final data phase.
14 IRDY# input Initiator ready, indicating the bus master's ability to complete the current data phase.
15 TRDY# tri_state Target ready, indicating the target's ability to complete the current data phase (sustained tri-state).
16 DEVSEL# tri_state Device select, driven when the device has decoded its address as the current access target (sustained tri-state).
17 STOP# tri_state Indicates the current target is requesting the master to stop the current transaction (sustained tri-state).
18 LOCK# input Indicates an atomic operation that may require multiple transactions to complete.
19 PERR# tri_state Reports data parity errors during all PCI transactions except a Special cycle (sustained tri-state).
20 SERR# output Reports address parity errors, data parity errors on Special Cycle, or other catastrophic system errors (open drain).
21 PAR bidirectional Even parity across AD[31:0] and C/BE[3:0]#, stable one clock after the address phase and valid per the PCI data phase timing.
22 C/BE1# input PCI bus command during address phase and byte enable 1 during data phase.
23 AD15 bidirectional PCI multiplexed address/data bit 15 (AD[31:0] bus, address phase then data phases).
24 AD14 bidirectional PCI multiplexed address/data bit 14 (AD[31:0] bus, address phase then data phases).
25 AD13 bidirectional PCI multiplexed address/data bit 13 (AD[31:0] bus, address phase then data phases).
26 VSS power_in Ground pin.
27 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
28 AD12 bidirectional PCI multiplexed address/data bit 12 (AD[31:0] bus, address phase then data phases).
29 AD11 bidirectional PCI multiplexed address/data bit 11 (AD[31:0] bus, address phase then data phases).
30 AD10 bidirectional PCI multiplexed address/data bit 10 (AD[31:0] bus, address phase then data phases).
31 AD9 bidirectional PCI multiplexed address/data bit 9 (AD[31:0] bus, address phase then data phases).
32 AD8 bidirectional PCI multiplexed address/data bit 8 (AD[31:0] bus, address phase then data phases).
33 C/BE0# input PCI bus command during address phase and byte enable 0 during data phase.
34 AD7 bidirectional PCI multiplexed address/data bit 7 (AD[31:0] bus, address phase then data phases).
35 AD6 bidirectional PCI multiplexed address/data bit 6 (AD[31:0] bus, address phase then data phases).
36 AD5 bidirectional PCI multiplexed address/data bit 5 (AD[31:0] bus, address phase then data phases).
37 AD4 bidirectional PCI multiplexed address/data bit 4 (AD[31:0] bus, address phase then data phases).
38 AD3 bidirectional PCI multiplexed address/data bit 3 (AD[31:0] bus, address phase then data phases).
39 AD2 bidirectional PCI multiplexed address/data bit 2 (AD[31:0] bus, address phase then data phases).
40 VSS power_in Ground pin.
41 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
42 AD1 bidirectional PCI multiplexed address/data bit 1 (AD[31:0] bus, address phase then data phases).
43 AD0 bidirectional PCI multiplexed address/data bit 0 (AD[31:0] bus, address phase then data phases).
44 INTA# output PCI interrupt A request output (open drain).
45 NC unconnected No connect in Non-Multiplexed and Multiplexed modes; in ISA Interface mode this pin is CHRDY input and should be pulled high.
46 LBE3# tri_state Local byte enable 3 (LAD[31:24] in 32-bit bus; BHE#/LAD[15:8] in 16-bit bus); in ISA mode it is SBHE# for Local Address Spaces 0 and 1.
47 LBE2# tri_state Local byte enable 2 (LAD[23:16] in 32-bit bus); not used in 16-bit or 8-bit bus modes.
48 LBE1# tri_state Local byte enable 1 (LAD[15:8] in 32-bit bus; LA1 in 16-bit and 8-bit bus modes); in ISA mode it is ISAA1.
49 LBE0# tri_state Local byte enable 0 (LAD[7:0]; BLE# in 16-bit bus, LA0 in 8-bit bus); in ISA mode it is ISAA0.
50 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
51 VSS power_in Ground pin.
52 LAD31 bidirectional Local multiplexed data bus bit 31 (32-bit bus width); carries data during the data phase.
53 LAD30 bidirectional Local multiplexed data bus bit 30 (32-bit bus width); carries data during the data phase.
54 LAD29 bidirectional Local multiplexed data bus bit 29 (32-bit bus width); carries data during the data phase.
55 LAD28 bidirectional Local multiplexed data bus bit 28 (32-bit bus width); carries data during the data phase.
56 LAD27 bidirectional Local multiplexed data bus bit 27 (32-bit bus width); carries data during the data phase.
57 LAD26 bidirectional Local multiplexed data bus bit 26 (32-bit bus width); carries data during the data phase.
58 LAD25 bidirectional Local multiplexed data bus bit 25 (32-bit bus width); carries data during the data phase.
59 LAD24 bidirectional Local multiplexed data bus bit 24 (32-bit bus width); carries data during the data phase.
60 LAD23 bidirectional Local multiplexed data bus bit 23 (32-bit bus width); carries data during the data phase.
61 LAD22 bidirectional Local multiplexed data bus bit 22 (32-bit bus width); carries data during the data phase.
62 LAD21 bidirectional Local multiplexed data bus bit 21 (32-bit bus width); carries data during the data phase.
63 BCLKO output Buffered version of the PCI clock for optional Local Bus use (24 mA totem pole); not in phase with the PCI clock.
64 ALE tri_state Address latch enable, asserted during the address phase and de-asserted before the data phase; pulse width depends on LCLK frequency (BALE in ISA mode for spaces 0 and 1).
65 VSS power_in Ground pin.
66 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
67 NC unconnected No connect in Non-Multiplexed and Multiplexed modes; in ISA Interface mode this pin is NOWS# input, held high by an internal 80 kΩ pull-up and can be tied high or left open otherwise.
68 MODE input Bus mode select: 0 = Non-Multiplexed mode, 1 = Multiplexed mode; must be 0 for ISA Interface mode.
69 LAD20 bidirectional Local multiplexed data bus bit 20 (16/32-bit bus width); carries data during the data phase.
70 LAD19 bidirectional Local multiplexed data bus bit 19 (16/32-bit bus width); carries data during the data phase.
71 LAD18 bidirectional Local multiplexed data bus bit 18 (16/32-bit bus width); carries data during the data phase.
72 LAD17 bidirectional Local multiplexed data bus bit 17 (16/32-bit bus width); carries data during the data phase.
73 LAD16 bidirectional Local multiplexed data bus bit 16 (16/32-bit bus width); carries data during the data phase.
74 LAD15 bidirectional Local data bus bit 15 (16-bit and 32-bit bus width); carries data during the data phase.
75 LAD14 bidirectional Local data bus bit 14 (16-bit and 32-bit bus width); carries data during the data phase.
76 LAD13 bidirectional Local data bus bit 13 (16-bit and 32-bit bus width); carries data during the data phase.
77 LAD12 bidirectional Local data bus bit 12 (16-bit and 32-bit bus width); carries data during the data phase.
78 LAD11 bidirectional Local data bus bit 11 (16-bit and 32-bit bus width); carries data during the data phase.
79 LAD10 bidirectional Local data bus bit 10 (16-bit and 32-bit bus width); carries data during the data phase.
80 VSS power_in Ground pin.
81 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
82 LAD9 bidirectional Local data bus bit 9 (16-bit and 32-bit bus width); carries data during the data phase.
83 LAD8 bidirectional Local data bus bit 8 (16-bit and 32-bit bus width); carries data during the data phase.
84 LAD7 bidirectional Local data bus bit 7 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
85 LAD6 bidirectional Local data bus bit 6 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
86 LAD5 bidirectional Local data bus bit 5 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
87 LAD4 bidirectional Local data bus bit 4 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
88 LAD3 bidirectional Local data bus bit 3 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
89 LAD2 bidirectional Local data bus bit 2 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
90 LAD1 bidirectional Local data bus bit 1 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
91 LAD0 bidirectional Local data bus bit 0 (8-bit, 16-bit and 32-bit bus width); carries data during the data phase.
92 LA2 tri_state Local address bus bit 2 (upper 26 bits of the 28-bit physical address, LA[27:2]); increments during bursts.
93 LA3 tri_state Local address bus bit 3 (LA[27:2]); increments during bursts.
94 LA4 tri_state Local address bus bit 4 (LA[27:2]); increments during bursts.
95 LA5 tri_state Local address bus bit 5 (LA[27:2]); increments during bursts.
96 LA6 tri_state Local address bus bit 6 (LA[27:2]); increments during bursts.
97 LA7 tri_state Local address bus bit 7 (LA[27:2]); increments during bursts.
98 LA8 tri_state Local address bus bit 8 (LA[27:2]); increments during bursts.
99 TEST input Test pin: tie low for normal operation; pulling high places all outputs except RD# in high impedance.
100 LA9 tri_state Local address bus bit 9 (LA[27:2]); increments during bursts.
101 LA10 tri_state Local address bus bit 10 (LA[27:2]); increments during bursts.
102 LA11 tri_state Local address bus bit 11 (LA[27:2]); increments during bursts.
103 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
104 VSS power_in Ground pin.
105 LA12 tri_state Local address bus bit 12 (LA[27:2]); increments during bursts.
106 LA13 tri_state Local address bus bit 13 (LA[27:2]); increments during bursts.
107 LA14 tri_state Local address bus bit 14 (LA[27:2]); increments during bursts.
108 LA15 tri_state Local address bus bit 15 (LA[27:2]); increments during bursts.
109 LA16 tri_state Local address bus bit 16 (LA[27:2]); increments during bursts.
110 LA17 tri_state Local address bus bit 17 (LA[27:2]); increments during bursts.
111 LA18 tri_state Local address bus bit 18 (LA[27:2]); increments during bursts.
112 LA19 tri_state Local address bus bit 19 (LA[27:2]); increments during bursts.
113 LA20 tri_state Local address bus bit 20 (LA[27:2]); increments during bursts.
114 LA21 tri_state Local address bus bit 21 (LA[27:2]); increments during bursts.
115 LA22 tri_state Local address bus bit 22 (LA[27:2]); increments during bursts.
116 LA23 tri_state Local address bus bit 23 (LA[27:2]); increments during bursts.
117 LA24 tri_state Local address bus bit 24 (LA[27:2]); increments during bursts.
118 LA25 tri_state Local address bus bit 25 (LA[27:2]); increments during bursts.
119 LA26 tri_state Local address bus bit 26 (LA[27:2]); increments during bursts.
120 VSS power_in Ground pin.
121 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
122 LA27 tri_state Local address bus bit 27, the most significant bit of the 28-bit physical address (LA[27:2]).
123 ADS# tri_state Address strobe, asserted for the first clock of a local bus access to indicate a valid address (12 mA).
124 BLAST# tri_state Burst last, driven by the local bus master to indicate the last transfer; not asserted until internal wait states expire.
125 WR# tri_state General purpose write strobe, timing controlled by the current Bus Region Descriptor register (12 mA).
126 RD# tri_state General purpose read strobe, timing controlled by the current Bus Region Descriptor; provides NAND tree output when TEST is high (12 mA).
127 LW/R# tri_state Local write/read indicator, asserted low for reads and high for writes.
128 LRDYi# input Local ready input indicating read data is on the local bus or write data is accepted; sampled only after internal wait states expire; internal 80 kΩ pull-up.
129 BTERM# input Burst terminate ready input that breaks a burst and forces a new address cycle when enabled; internal 80 kΩ pull-up.
130 CS0# tri_state General purpose chip select 0 with programmable base and range; redefined as MEMRD# in ISA Interface mode (8 mA).
131 CS1# tri_state General purpose chip select 1 with programmable base and range; redefined as MEMWR# in ISA Interface mode (8 mA).
132 LRESET# output Local reset output asserted when the PCI 9052 is reset; inverted to LRESET (active high) in ISA Interface mode (8 mA totem pole).
133 LHOLDA output Hold acknowledge asserted to grant local bus control to a local bus master; de-asserted to preempt when the PCI 9052 needs the bus (8 mA totem pole).
134 LHOLD input Hold request from a local bus master; pull or drive low to make the PCI 9052 local bus master (no internal pull resistor).
135 LCLK input Local clock input, required, up to 40 MHz, may be asynchronous to the PCI clock.
136 LINTi2 input Local interrupt 2 input, programmable active-low or active-high level-sensitive (or edge-triggered) interrupt that can assert INTA#.
137 LINTi1 input Local interrupt 1 input, programmable active-low or active-high level-sensitive (or edge-triggered) interrupt that can assert INTA#.
138 USER0/WAITO# bidirectional Configurable user I/O 0 or WAIT output (WAITO#); default is USER0 input, redefined as IORD# in ISA Interface mode (8 mA).
139 USER1/LLOCKo# bidirectional Configurable user I/O 1 or LLOCK output (LLOCKo#); default is USER1 input, redefined as IOWR# in ISA Interface mode (8 mA).
140 USER2/CS2# bidirectional Configurable user I/O 2 or chip select 2 output (CS2#); default is USER2 input (8 mA).
141 USER3/CS3# bidirectional Configurable user I/O 3 or chip select 3 output (CS3#); default is USER3 input (8 mA).
142 EECS output Serial EEPROM chip select output (8 mA totem pole).
143 EEDO input Serial EEPROM data out (read data from EEPROM); requires an external pull-up if no or a blank EEPROM is used.
144 EESK output Serial EEPROM clock output (8 mA totem pole).
145 EEDI output Serial EEPROM data in (write data to EEPROM) output (8 mA totem pole).
146 VDD power_in Power supply pin (5 V); place .01 to .1 µF decoupling capacitors near the PCI 9052.
147 VSS power_in Ground pin.
148 RST# input PCI reset input that brings PCI-specific registers, sequencers and signals to a consistent state.
149 CLK input PCI clock providing timing for all PCI transactions; operates up to 33 MHz.
150 AD31 bidirectional PCI multiplexed address/data bit 31 (AD[31:0] bus, address phase then data phases).
151 AD30 bidirectional PCI multiplexed address/data bit 30 (AD[31:0] bus, address phase then data phases).
152 AD29 bidirectional PCI multiplexed address/data bit 29 (AD[31:0] bus, address phase then data phases).
153 AD28 bidirectional PCI multiplexed address/data bit 28 (AD[31:0] bus, address phase then data phases).
154 AD27 bidirectional PCI multiplexed address/data bit 27 (AD[31:0] bus, address phase then data phases).
155 AD26 bidirectional PCI multiplexed address/data bit 26 (AD[31:0] bus, address phase then data phases).
156 AD25 bidirectional PCI multiplexed address/data bit 25 (AD[31:0] bus, address phase then data phases).
157 AD24 bidirectional PCI multiplexed address/data bit 24 (AD[31:0] bus, address phase then data phases).
158 C/BE3# input PCI bus command during address phase and byte enable 3 during data phase.
159 IDSEL input Initialization device select, used as chip select during PCI configuration read or write transactions.
160 VSS power_in Ground pin.

Key specifications

Parameter Value
Manufacturer Broadcom Limited
Package PQFP-160(28x28)
Category Interface
Pins 160

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output High Voltage VOH 2.4 V VDD = Min, VIN = VIH or VIL, IOH = -4.0 mA 150
Output Low Voltage VOL 0.4 V IOL = per Tables 9-6 and 9-8 through 9-11 150
Input High Level VIH 2 V 150
Input Low Level VIL 0.8 V 150
Input Leakage Current ILI -10 10 μA VSS ≤ VIN ≤ VDD, VDD = Max 150
Tri-State Output Leakage Current IOZ -10 10 μA VSS ≤ VIN ≤ VDD, VDD = Max 150
Power Supply Current ICC 130 mA VDD = 5.25V, PCLK = LCLK = 33 MHz 150
Local Clock Input frequency 0 40 MHz 150
PCI Clock Input frequency 0 33 MHz 150
TVALID Local output ADS# ADS# 3 7.4 10 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output BCLKO BCLKO 2 7 8 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output BLAST# BLAST# 5 9.4 16 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output CS[3:0]# CS[3:0]# 4 11 17 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LA[27:2] LA[27:2] 5 14 18.6 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LAD[31:0] LAD[31:0] 5 14.6 16 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LBE[3:0]# LBE[3:0]# 4 8.4 15 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LHOLDA LHOLDA 3 9 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LRESET# LRESET# 5 14 17 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output LW/R# LW/R# 4 7.8 12 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output RD# RD# 7 13 16 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output USER[3:0] USER[3:0] 4 5 12 ns CL = 50 pF, VCC = 5.0 ±5% 151
TVALID Local output WR# WR# 4 9 13 ns CL = 50 pF, VCC = 5.0 ±5% 151
Storage Temperature -65 150 °C 149
Ambient Temperature with Power Applied -55 125 °C 149
Supply Voltage to Ground VDD -0.5 7 V 149
Maximum Package Power Dissipation 0.65 W 1.0 m/s air flow 149
Ambient Temperature (operating) -40 85 °C 149
Junction Temperature (operating) 115 °C 149
Supply Voltage tolerance (VDD 5V ±5%) VDD -5 5 % 149
Supply Voltage (VDD) nominal VDD 5 V 149
Package thermal resistance θJA, QFP 160L 28x28 ΘJA 65 °C/W Ta = 85°C, 0 m/s air flow 149
Package thermal resistance θJA, QFP 160L 28x28 ΘJA 45 °C/W Ta = 85°C, 1 m/s air flow 149
Package thermal resistance θJA, QFP 160L 28x28 ΘJA 34 °C/W Ta = 85°C, 2 m/s air flow 149

CAD (KiCad official)

  • Symbol: PCI9052G
  • Footprint: Package_QFP:PQFP-160_28x28mm_P0.65mm
  • 3D model: PQFP-160(28x28) (KiCad packages3D, STEP)
  • 3D model files: pci9052g-etched.step / pci9052g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pci9052g.step / pci9052g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Broadcom Limited datasheet (160 pp, sha256 aced364bc8bfdc5b, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF