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PCI2050BPDV

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Texas Instruments Interface - Specialized, LQFP-208(28x28). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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PCI2050BPDV

Texas Instruments · Interface - Specialized · LQFP-208(28x28)

PCI2050BPDV from Texas Instruments, in a LQFP-208(28x28). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Power-supply terminal for core logic (3.3 V).
2 S_REQ1 input Secondary PCI bus request input from secondary master 1; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
3 S_REQ2 input Secondary PCI bus request input from secondary master 2; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
4 S_REQ3 input Secondary PCI bus request input from secondary master 3; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
5 S_REQ4 input Secondary PCI bus request input from secondary master 4; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
6 S_REQ5 input Secondary PCI bus request input from secondary master 5; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
7 S_REQ6 input Secondary PCI bus request input from secondary master 6; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
8 S_REQ7 input Secondary PCI bus request input from secondary master 7; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
9 S_REQ8 input Secondary PCI bus request input from secondary master 8; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus.
10 S_GNT0 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
11 S_GNT1 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
12 GND power_in Device ground terminal.
13 S_GNT2 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
14 S_GNT3 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
15 S_GNT4 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
16 S_GNT5 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
17 S_GNT6 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
18 S_GNT7 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
19 S_GNT8 output Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1).
20 GND power_in Device ground terminal.
21 S_CLK input Secondary PCI bus clock input; function not stated in the provided excerpt beyond the signal name.
22 S_RST input Secondary PCI bus reset; function not stated in the provided excerpt beyond the signal name.
23 S_CFN input Secondary configuration-function signal; function not stated in the provided excerpt beyond the signal name.
24 HS_SWITCH/GPIO3 input General-purpose I/O 3; in cPCI mode it is HS_SWITCH, which provides the status of the ejector handle switch to the cPCI logic.
25 GPIO2 bidirectional General-purpose I/O terminal; no further detail given in the provided excerpt.
26 VCC power_in Power-supply terminal for core logic (3.3 V).
27 GPIO1 bidirectional General-purpose I/O terminal; no further detail given in the provided excerpt.
28 GPIO0 bidirectional General-purpose I/O terminal; no further detail given in the provided excerpt.
29 S_CLKOUT0 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
30 S_CLKOUT1 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
31 GND power_in Device ground terminal.
32 S_CLKOUT2 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
33 S_CLKOUT3 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
34 VCC power_in Power-supply terminal for core logic (3.3 V).
35 S_CLKOUT4 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
36 S_CLKOUT5 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
37 GND power_in Device ground terminal.
38 S_CLKOUT6 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
39 S_CLKOUT7 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
40 VCC power_in Power-supply terminal for core logic (3.3 V).
41 S_CLKOUT8 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
42 S_CLKOUT9 output Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name.
43 P_RST input Primary PCI bus reset; function not stated in the provided excerpt beyond the signal name.
44 BPCCE input Bus/power clock control enable; when tied high and the device is in D3, the secondary clocks are disabled and driven to 0 to allow the secondary bus to enter B2, and when tied low D3 has no effect on secondary clocks.
45 P_CLK input Primary PCI bus clock input; function not stated in the provided excerpt beyond the signal name.
46 P_GNT input Primary PCI bus grant input; function not stated in the provided excerpt beyond the signal name.
47 P_REQ output Primary PCI bus request output; function not stated in the provided excerpt beyond the signal name.
48 GND power_in Device ground terminal.
49 P_AD31 bidirectional Primary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name.
50 P_AD30 bidirectional Primary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name.
51 VCC power_in Power-supply terminal for core logic (3.3 V).
52 GND power_in Device ground terminal.
53 VCC power_in Power-supply terminal for core logic (3.3 V).
54 GND power_in Device ground terminal.
55 P_AD29 bidirectional Primary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name.
56 VCC power_in Power-supply terminal for core logic (3.3 V).
57 P_AD28 bidirectional Primary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name.
58 P_AD27 bidirectional Primary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name.
59 GND power_in Device ground terminal.
60 P_AD26 bidirectional Primary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name.
61 P_AD25 bidirectional Primary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name.
62 VCC power_in Power-supply terminal for core logic (3.3 V).
63 P_AD24 bidirectional Primary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name.
64 P_C/BE3 bidirectional Primary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name.
65 P_IDSEL input Primary PCI initialization device select; function not stated in the provided excerpt beyond the signal name.
66 GND power_in Device ground terminal.
67 P_AD23 bidirectional Primary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name.
68 P_AD22 bidirectional Primary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name.
69 VCC power_in Power-supply terminal for core logic (3.3 V).
70 P_AD21 bidirectional Primary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name.
71 P_AD20 bidirectional Primary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name.
72 GND power_in Device ground terminal.
73 P_AD19 bidirectional Primary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name.
74 P_AD18 bidirectional Primary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name.
75 VCC power_in Power-supply terminal for core logic (3.3 V).
76 P_AD17 bidirectional Primary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name.
77 P_AD16 bidirectional Primary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name.
78 GND power_in Device ground terminal.
79 P_C/BE2 bidirectional Primary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name.
80 P_FRAME bidirectional Primary PCI cycle frame; function not stated in the provided excerpt beyond the signal name.
81 VCC power_in Power-supply terminal for core logic (3.3 V).
82 P_IRDY bidirectional Primary PCI initiator ready; function not stated in the provided excerpt beyond the signal name.
83 P_TRDY bidirectional Primary PCI target ready; function not stated in the provided excerpt beyond the signal name.
84 P_DEVSEL bidirectional Primary PCI device select; function not stated in the provided excerpt beyond the signal name.
85 P_STOP bidirectional Primary PCI cycle stop; function not stated in the provided excerpt beyond the signal name.
86 GND power_in Device ground terminal.
87 P_LOCK bidirectional Primary PCI bus lock; function not stated in the provided excerpt beyond the signal name.
88 P_PERR bidirectional Primary PCI parity error indicator; function not stated in the provided excerpt beyond the signal name.
89 P_SERR bidirectional Primary PCI system error; function not stated in the provided excerpt beyond the signal name.
90 P_PAR bidirectional Primary PCI parity; function not stated in the provided excerpt beyond the signal name.
91 VCC power_in Power-supply terminal for core logic (3.3 V).
92 P_C/BE1 bidirectional Primary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name.
93 P_AD15 bidirectional Primary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name.
94 GND power_in Device ground terminal.
95 P_AD14 bidirectional Primary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name.
96 P_AD13 bidirectional Primary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name.
97 VCC power_in Power-supply terminal for core logic (3.3 V).
98 P_AD12 bidirectional Primary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name.
99 P_AD11 bidirectional Primary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name.
100 GND power_in Device ground terminal.
101 P_AD10 bidirectional Primary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name.
102 P_M66ENA input Primary interface 66 MHz enable, input-only; must be pulled low for 33-MHz primary operation (which forces the secondary bus to 33 MHz) and pulled high for 66-MHz operation.
103 VCC power_in Power-supply terminal for core logic (3.3 V).
104 GND power_in Device ground terminal.
105 VCC power_in Power-supply terminal for core logic (3.3 V).
106 MS1 input Mode select 1 input; the provided excerpt names the pin but does not give its detailed function.
107 P_AD9 bidirectional Primary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name.
108 VCC power_in Power-supply terminal for core logic (3.3 V).
109 P_AD8 bidirectional Primary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name.
110 P_C/BE0 bidirectional Primary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name.
111 GND power_in Device ground terminal.
112 P_AD7 bidirectional Primary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name.
113 P_AD6 bidirectional Primary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name.
114 VCC power_in Power-supply terminal for core logic (3.3 V).
115 P_AD5 bidirectional Primary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name.
116 P_AD4 bidirectional Primary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name.
117 GND power_in Device ground terminal.
118 P_AD3 bidirectional Primary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name.
119 P_AD2 bidirectional Primary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name.
120 VCC power_in Power-supply terminal for core logic (3.3 V).
121 P_AD1 bidirectional Primary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name.
122 P_AD0 bidirectional Primary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name.
123 GND power_in Device ground terminal.
124 P_VCCP power_in Primary bus-signaling environment supply used in protection circuitry on primary bus I/O signals; TI recommends powering P_VCCP and S_VCCP up before VCC.
125 CONFIG66 input Input-only configuration of 66 MHz capability; tied high allows 66 MHz operation, tied low restricts the device to 33-MHz PCI operation.
126 MSK_IN input Secondary clock mask input; function not stated in the provided excerpt beyond the signal name.
127 HS_ENUM output Hot-swap ENUM output.
128 HS_LED output Hot-swap LED output.
129 TDI input JTAG serial data input; instructions and test data enter here and are sampled on the rising edge of TCK.
130 TDO output JTAG serial data output through which test instructions and data leave the device.
131 VCC power_in Power-supply terminal for core logic (3.3 V).
132 TMS input JTAG test mode select; causes state transitions in the test access port controller.
133 TCK input JTAG boundary-scan clock that controls the JTAG logic.
134 TRST input JTAG TAP reset; when asserted low it asynchronously forces the TAP controller into reset and initializes the test logic.
135 S_VCCP power_in Secondary bus-signaling environment supply used in protection circuitry on secondary bus I/O signals; TI recommends powering S_VCCP up before VCC.
136 GND power_in Device ground terminal.
137 S_AD0 bidirectional Secondary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name.
138 S_AD1 bidirectional Secondary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name.
139 VCC power_in Power-supply terminal for core logic (3.3 V).
140 S_AD2 bidirectional Secondary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name.
141 S_AD3 bidirectional Secondary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name.
142 GND power_in Device ground terminal.
143 S_AD4 bidirectional Secondary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name.
144 S_AD5 bidirectional Secondary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name.
145 VCC power_in Power-supply terminal for core logic (3.3 V).
146 S_AD6 bidirectional Secondary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name.
147 S_AD7 bidirectional Secondary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name.
148 GND power_in Device ground terminal.
149 S_C/BE0 bidirectional Secondary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name.
150 S_AD8 bidirectional Secondary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name.
151 VCC power_in Power-supply terminal for core logic (3.3 V).
152 S_AD9 bidirectional Secondary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name.
153 S_M66ENA bidirectional Secondary 66 MHz enable, open-drain; driven low by the device when P_M66ENA is low, and when the primary bus runs at 66 MHz it must be pulled high for 66-MHz or low for 33-MHz secondary operation.
154 S_AD10 bidirectional Secondary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name.
155 MS0 input Mode select 0 input; the provided excerpt names the pin but does not give its detailed function.
156 GND power_in Device ground terminal.
157 VCC power_in Power-supply terminal for core logic (3.3 V).
158 GND power_in Device ground terminal.
159 S_AD11 bidirectional Secondary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name.
160 GND power_in Device ground terminal.
161 S_AD12 bidirectional Secondary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name.
162 S_AD13 bidirectional Secondary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name.
163 VCC power_in Power-supply terminal for core logic (3.3 V).
164 S_AD14 bidirectional Secondary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name.
165 S_AD15 bidirectional Secondary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name.
166 GND power_in Device ground terminal.
167 S_C/BE1 bidirectional Secondary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name.
168 S_PAR bidirectional Secondary parity; the bridge calculates even parity across S_AD and S_C/BE in all secondary read and write cycles, driving it one S_CLK later as master on writes.
169 S_SERR input Secondary system error, passed through to the primary interface when enabled; the bridge never asserts it.
170 VCC power_in Power-supply terminal for core logic (3.3 V).
171 S_PERR bidirectional Secondary parity error indicator, driven by a secondary device when calculated parity does not match S_PAR and it is enabled in the command register.
172 S_LOCK bidirectional Secondary PCI bus lock used to lock the secondary bus and gain exclusive access as a master.
173 S_STOP bidirectional Secondary cycle stop signal driven by a PCI target to request that the master stop the current transaction (used for target disconnects).
174 GND power_in Device ground terminal.
175 S_DEVSEL bidirectional Secondary device select; function not stated in the provided excerpt beyond the signal name.
176 S_TRDY bidirectional Secondary target ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then.
177 S_IRDY bidirectional Secondary initiator ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then.
178 VCC power_in Power-supply terminal for core logic (3.3 V).
179 S_FRAME bidirectional Secondary cycle frame; function not stated in the provided excerpt beyond the signal name.
180 S_C/BE2 bidirectional Secondary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name.
181 GND power_in Device ground terminal.
182 S_AD16 bidirectional Secondary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name.
183 S_AD17 bidirectional Secondary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name.
184 VCC power_in Power-supply terminal for core logic (3.3 V).
185 S_AD18 bidirectional Secondary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name.
186 S_AD19 bidirectional Secondary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name.
187 GND power_in Device ground terminal.
188 S_AD20 bidirectional Secondary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name.
189 S_AD21 bidirectional Secondary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name.
190 VCC power_in Power-supply terminal for core logic (3.3 V).
191 S_AD22 bidirectional Secondary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name.
192 S_AD23 bidirectional Secondary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name.
193 GND power_in Device ground terminal.
194 S_C/BE3 bidirectional Secondary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name.
195 S_AD24 bidirectional Secondary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name.
196 VCC power_in Power-supply terminal for core logic (3.3 V).
197 S_AD25 bidirectional Secondary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name.
198 S_AD26 bidirectional Secondary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name.
199 GND power_in Device ground terminal.
200 S_AD27 bidirectional Secondary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name.
201 S_AD28 bidirectional Secondary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name.
202 VCC power_in Power-supply terminal for core logic (3.3 V).
203 S_AD29 bidirectional Secondary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name.
204 S_AD30 bidirectional Secondary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name.
205 GND power_in Device ground terminal.
206 S_AD31 bidirectional Secondary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name.
207 S_REQ0 input Secondary PCI bus request input from secondary master 0; when the internal arbiter is disabled this pin is reconfigured as an external secondary bus grant for the bridge.
208 VCC power_in Power-supply terminal for core logic (3.3 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-208(28x28)
Category Communication Interface Chip/UART/485/232
Pins 208

CAD (KiCad official)

  • Symbol: PCI2050BPDV
  • Footprint: Package_QFP:LQFP-208_28x28mm_P0.5mm
  • 3D model: LQFP-208(28x28) (KiCad packages3D, STEP)
  • 3D model files: pci2050bpdv-etched.step / pci2050bpdv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pci2050bpdv.step / pci2050bpdv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 879d9875d1ecefb1, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF