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PCI2050BPDV
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Texas Instruments Interface - Specialized, LQFP-208(28x28). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+244@@ -0,0 +1,244 @@+# PCI2050BPDV++**Texas Instruments** · Interface - Specialized · LQFP-208(28x28)++PCI2050BPDV from Texas Instruments, in a LQFP-208(28x28). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 2 | S_REQ1 | input | Secondary PCI bus request input from secondary master 1; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 3 | S_REQ2 | input | Secondary PCI bus request input from secondary master 2; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 4 | S_REQ3 | input | Secondary PCI bus request input from secondary master 3; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 5 | S_REQ4 | input | Secondary PCI bus request input from secondary master 4; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 6 | S_REQ5 | input | Secondary PCI bus request input from secondary master 5; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 7 | S_REQ6 | input | Secondary PCI bus request input from secondary master 6; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 8 | S_REQ7 | input | Secondary PCI bus request input from secondary master 7; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 9 | S_REQ8 | input | Secondary PCI bus request input from secondary master 8; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus. |+| 10 | S_GNT0 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 11 | S_GNT1 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 12 | GND | power_in | Device ground terminal. |+| 13 | S_GNT2 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 14 | S_GNT3 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 15 | S_GNT4 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 16 | S_GNT5 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 17 | S_GNT6 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 18 | S_GNT7 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 19 | S_GNT8 | output | Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1). |+| 20 | GND | power_in | Device ground terminal. |+| 21 | S_CLK | input | Secondary PCI bus clock input; function not stated in the provided excerpt beyond the signal name. |+| 22 | S_RST | input | Secondary PCI bus reset; function not stated in the provided excerpt beyond the signal name. |+| 23 | S_CFN | input | Secondary configuration-function signal; function not stated in the provided excerpt beyond the signal name. |+| 24 | HS_SWITCH/GPIO3 | input | General-purpose I/O 3; in cPCI mode it is HS_SWITCH, which provides the status of the ejector handle switch to the cPCI logic. |+| 25 | GPIO2 | bidirectional | General-purpose I/O terminal; no further detail given in the provided excerpt. |+| 26 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 27 | GPIO1 | bidirectional | General-purpose I/O terminal; no further detail given in the provided excerpt. |+| 28 | GPIO0 | bidirectional | General-purpose I/O terminal; no further detail given in the provided excerpt. |+| 29 | S_CLKOUT0 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 30 | S_CLKOUT1 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 31 | GND | power_in | Device ground terminal. |+| 32 | S_CLKOUT2 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 33 | S_CLKOUT3 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 34 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 35 | S_CLKOUT4 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 36 | S_CLKOUT5 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 37 | GND | power_in | Device ground terminal. |+| 38 | S_CLKOUT6 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 39 | S_CLKOUT7 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 40 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 41 | S_CLKOUT8 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 42 | S_CLKOUT9 | output | Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name. |+| 43 | P_RST | input | Primary PCI bus reset; function not stated in the provided excerpt beyond the signal name. |+| 44 | BPCCE | input | Bus/power clock control enable; when tied high and the device is in D3, the secondary clocks are disabled and driven to 0 to allow the secondary bus to enter B2, and when tied low D3 has no effect on secondary clocks. |+| 45 | P_CLK | input | Primary PCI bus clock input; function not stated in the provided excerpt beyond the signal name. |+| 46 | P_GNT | input | Primary PCI bus grant input; function not stated in the provided excerpt beyond the signal name. |+| 47 | P_REQ | output | Primary PCI bus request output; function not stated in the provided excerpt beyond the signal name. |+| 48 | GND | power_in | Device ground terminal. |+| 49 | P_AD31 | bidirectional | Primary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name. |+| 50 | P_AD30 | bidirectional | Primary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name. |+| 51 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 52 | GND | power_in | Device ground terminal. |+| 53 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 54 | GND | power_in | Device ground terminal. |+| 55 | P_AD29 | bidirectional | Primary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name. |+| 56 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 57 | P_AD28 | bidirectional | Primary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name. |+| 58 | P_AD27 | bidirectional | Primary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name. |+| 59 | GND | power_in | Device ground terminal. |+| 60 | P_AD26 | bidirectional | Primary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name. |+| 61 | P_AD25 | bidirectional | Primary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name. |+| 62 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 63 | P_AD24 | bidirectional | Primary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name. |+| 64 | P_C/BE3 | bidirectional | Primary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name. |+| 65 | P_IDSEL | input | Primary PCI initialization device select; function not stated in the provided excerpt beyond the signal name. |+| 66 | GND | power_in | Device ground terminal. |+| 67 | P_AD23 | bidirectional | Primary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name. |+| 68 | P_AD22 | bidirectional | Primary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name. |+| 69 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 70 | P_AD21 | bidirectional | Primary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name. |+| 71 | P_AD20 | bidirectional | Primary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name. |+| 72 | GND | power_in | Device ground terminal. |+| 73 | P_AD19 | bidirectional | Primary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name. |+| 74 | P_AD18 | bidirectional | Primary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name. |+| 75 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 76 | P_AD17 | bidirectional | Primary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name. |+| 77 | P_AD16 | bidirectional | Primary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name. |+| 78 | GND | power_in | Device ground terminal. |+| 79 | P_C/BE2 | bidirectional | Primary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name. |+| 80 | P_FRAME | bidirectional | Primary PCI cycle frame; function not stated in the provided excerpt beyond the signal name. |+| 81 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 82 | P_IRDY | bidirectional | Primary PCI initiator ready; function not stated in the provided excerpt beyond the signal name. |+| 83 | P_TRDY | bidirectional | Primary PCI target ready; function not stated in the provided excerpt beyond the signal name. |+| 84 | P_DEVSEL | bidirectional | Primary PCI device select; function not stated in the provided excerpt beyond the signal name. |+| 85 | P_STOP | bidirectional | Primary PCI cycle stop; function not stated in the provided excerpt beyond the signal name. |+| 86 | GND | power_in | Device ground terminal. |+| 87 | P_LOCK | bidirectional | Primary PCI bus lock; function not stated in the provided excerpt beyond the signal name. |+| 88 | P_PERR | bidirectional | Primary PCI parity error indicator; function not stated in the provided excerpt beyond the signal name. |+| 89 | P_SERR | bidirectional | Primary PCI system error; function not stated in the provided excerpt beyond the signal name. |+| 90 | P_PAR | bidirectional | Primary PCI parity; function not stated in the provided excerpt beyond the signal name. |+| 91 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 92 | P_C/BE1 | bidirectional | Primary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name. |+| 93 | P_AD15 | bidirectional | Primary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name. |+| 94 | GND | power_in | Device ground terminal. |+| 95 | P_AD14 | bidirectional | Primary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name. |+| 96 | P_AD13 | bidirectional | Primary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name. |+| 97 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 98 | P_AD12 | bidirectional | Primary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name. |+| 99 | P_AD11 | bidirectional | Primary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name. |+| 100 | GND | power_in | Device ground terminal. |+| 101 | P_AD10 | bidirectional | Primary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name. |+| 102 | P_M66ENA | input | Primary interface 66 MHz enable, input-only; must be pulled low for 33-MHz primary operation (which forces the secondary bus to 33 MHz) and pulled high for 66-MHz operation. |+| 103 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 104 | GND | power_in | Device ground terminal. |+| 105 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 106 | MS1 | input | Mode select 1 input; the provided excerpt names the pin but does not give its detailed function. |+| 107 | P_AD9 | bidirectional | Primary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name. |+| 108 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 109 | P_AD8 | bidirectional | Primary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name. |+| 110 | P_C/BE0 | bidirectional | Primary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name. |+| 111 | GND | power_in | Device ground terminal. |+| 112 | P_AD7 | bidirectional | Primary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name. |+| 113 | P_AD6 | bidirectional | Primary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name. |+| 114 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 115 | P_AD5 | bidirectional | Primary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name. |+| 116 | P_AD4 | bidirectional | Primary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name. |+| 117 | GND | power_in | Device ground terminal. |+| 118 | P_AD3 | bidirectional | Primary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name. |+| 119 | P_AD2 | bidirectional | Primary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name. |+| 120 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 121 | P_AD1 | bidirectional | Primary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name. |+| 122 | P_AD0 | bidirectional | Primary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name. |+| 123 | GND | power_in | Device ground terminal. |+| 124 | P_VCCP | power_in | Primary bus-signaling environment supply used in protection circuitry on primary bus I/O signals; TI recommends powering P_VCCP and S_VCCP up before VCC. |+| 125 | CONFIG66 | input | Input-only configuration of 66 MHz capability; tied high allows 66 MHz operation, tied low restricts the device to 33-MHz PCI operation. |+| 126 | MSK_IN | input | Secondary clock mask input; function not stated in the provided excerpt beyond the signal name. |+| 127 | HS_ENUM | output | Hot-swap ENUM output. |+| 128 | HS_LED | output | Hot-swap LED output. |+| 129 | TDI | input | JTAG serial data input; instructions and test data enter here and are sampled on the rising edge of TCK. |+| 130 | TDO | output | JTAG serial data output through which test instructions and data leave the device. |+| 131 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 132 | TMS | input | JTAG test mode select; causes state transitions in the test access port controller. |+| 133 | TCK | input | JTAG boundary-scan clock that controls the JTAG logic. |+| 134 | TRST | input | JTAG TAP reset; when asserted low it asynchronously forces the TAP controller into reset and initializes the test logic. |+| 135 | S_VCCP | power_in | Secondary bus-signaling environment supply used in protection circuitry on secondary bus I/O signals; TI recommends powering S_VCCP up before VCC. |+| 136 | GND | power_in | Device ground terminal. |+| 137 | S_AD0 | bidirectional | Secondary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name. |+| 138 | S_AD1 | bidirectional | Secondary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name. |+| 139 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 140 | S_AD2 | bidirectional | Secondary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name. |+| 141 | S_AD3 | bidirectional | Secondary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name. |+| 142 | GND | power_in | Device ground terminal. |+| 143 | S_AD4 | bidirectional | Secondary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name. |+| 144 | S_AD5 | bidirectional | Secondary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name. |+| 145 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 146 | S_AD6 | bidirectional | Secondary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name. |+| 147 | S_AD7 | bidirectional | Secondary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name. |+| 148 | GND | power_in | Device ground terminal. |+| 149 | S_C/BE0 | bidirectional | Secondary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name. |+| 150 | S_AD8 | bidirectional | Secondary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name. |+| 151 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 152 | S_AD9 | bidirectional | Secondary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name. |+| 153 | S_M66ENA | bidirectional | Secondary 66 MHz enable, open-drain; driven low by the device when P_M66ENA is low, and when the primary bus runs at 66 MHz it must be pulled high for 66-MHz or low for 33-MHz secondary operation. |+| 154 | S_AD10 | bidirectional | Secondary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name. |+| 155 | MS0 | input | Mode select 0 input; the provided excerpt names the pin but does not give its detailed function. |+| 156 | GND | power_in | Device ground terminal. |+| 157 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 158 | GND | power_in | Device ground terminal. |+| 159 | S_AD11 | bidirectional | Secondary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name. |+| 160 | GND | power_in | Device ground terminal. |+| 161 | S_AD12 | bidirectional | Secondary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name. |+| 162 | S_AD13 | bidirectional | Secondary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name. |+| 163 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 164 | S_AD14 | bidirectional | Secondary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name. |+| 165 | S_AD15 | bidirectional | Secondary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name. |+| 166 | GND | power_in | Device ground terminal. |+| 167 | S_C/BE1 | bidirectional | Secondary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name. |+| 168 | S_PAR | bidirectional | Secondary parity; the bridge calculates even parity across S_AD and S_C/BE in all secondary read and write cycles, driving it one S_CLK later as master on writes. |+| 169 | S_SERR | input | Secondary system error, passed through to the primary interface when enabled; the bridge never asserts it. |+| 170 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 171 | S_PERR | bidirectional | Secondary parity error indicator, driven by a secondary device when calculated parity does not match S_PAR and it is enabled in the command register. |+| 172 | S_LOCK | bidirectional | Secondary PCI bus lock used to lock the secondary bus and gain exclusive access as a master. |+| 173 | S_STOP | bidirectional | Secondary cycle stop signal driven by a PCI target to request that the master stop the current transaction (used for target disconnects). |+| 174 | GND | power_in | Device ground terminal. |+| 175 | S_DEVSEL | bidirectional | Secondary device select; function not stated in the provided excerpt beyond the signal name. |+| 176 | S_TRDY | bidirectional | Secondary target ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then. |+| 177 | S_IRDY | bidirectional | Secondary initiator ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then. |+| 178 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 179 | S_FRAME | bidirectional | Secondary cycle frame; function not stated in the provided excerpt beyond the signal name. |+| 180 | S_C/BE2 | bidirectional | Secondary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name. |+| 181 | GND | power_in | Device ground terminal. |+| 182 | S_AD16 | bidirectional | Secondary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name. |+| 183 | S_AD17 | bidirectional | Secondary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name. |+| 184 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 185 | S_AD18 | bidirectional | Secondary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name. |+| 186 | S_AD19 | bidirectional | Secondary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name. |+| 187 | GND | power_in | Device ground terminal. |+| 188 | S_AD20 | bidirectional | Secondary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name. |+| 189 | S_AD21 | bidirectional | Secondary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name. |+| 190 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 191 | S_AD22 | bidirectional | Secondary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name. |+| 192 | S_AD23 | bidirectional | Secondary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name. |+| 193 | GND | power_in | Device ground terminal. |+| 194 | S_C/BE3 | bidirectional | Secondary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name. |+| 195 | S_AD24 | bidirectional | Secondary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name. |+| 196 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 197 | S_AD25 | bidirectional | Secondary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name. |+| 198 | S_AD26 | bidirectional | Secondary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name. |+| 199 | GND | power_in | Device ground terminal. |+| 200 | S_AD27 | bidirectional | Secondary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name. |+| 201 | S_AD28 | bidirectional | Secondary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name. |+| 202 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |+| 203 | S_AD29 | bidirectional | Secondary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name. |+| 204 | S_AD30 | bidirectional | Secondary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name. |+| 205 | GND | power_in | Device ground terminal. |+| 206 | S_AD31 | bidirectional | Secondary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name. |+| 207 | S_REQ0 | input | Secondary PCI bus request input from secondary master 0; when the internal arbiter is disabled this pin is reconfigured as an external secondary bus grant for the bridge. |+| 208 | VCC | power_in | Power-supply terminal for core logic (3.3 V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-208(28x28) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 208 |++## CAD (KiCad official)++- Symbol: `PCI2050BPDV`+- Footprint: `Package_QFP:LQFP-208_28x28mm_P0.5mm`+- 3D model: LQFP-208(28x28) (KiCad packages3D, STEP)+- 3D model files: `pci2050bpdv-etched.step` / `pci2050bpdv-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `pci2050bpdv.step` / `pci2050bpdv.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/pci2050b) (89 pp, sha256 `879d9875d1ecefb1`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/pci2050bpdv-datasheet.pdf)
page.jsonadded+1401@@ -0,0 +1,1401 @@+{+ "slug": "pci2050bpdv",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Interface - Specialized, LQFP-208(28x28). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "pci2050bpdv",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "pci2050bpdv.kicad_sym",+ "pci2050bpdv.kicad_mod",+ "pci2050bpdv.glb",+ "pci2050bpdv.step",+ "pci2050bpdv.lbr",+ "docs/hero.png",+ "docs/pci2050bpdv-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "pci2050bpdv-hero.glb",+ "pci2050bpdv-hero.overlay.json"+ ],+ "component": {+ "mpn": "PCI2050BPDV",+ "manufacturer": "Texas Instruments",+ "package": "LQFP-208(28x28)",+ "pin_count": 208,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "Interface - Specialized",+ "datasheet": "https://www.ti.com/cn/lit/gpn/pci2050b",+ "parts": {+ "symbol": "pci2050bpdv.kicad_sym",+ "footprint": "pci2050bpdv.kicad_mod",+ "model_3d": "pci2050bpdv-hero.glb",+ "model_3d_plain": "pci2050bpdv.glb",+ "model_3d_step": "pci2050bpdv-etched.step",+ "model_3d_step_plain": "pci2050bpdv.step",+ "lbr": "pci2050bpdv.lbr"+ },+ "distributor_links": {+ "lcsc": "C544853",+ "digikey": "296-14347-ND",+ "mouser": "595-PCI2050BPDV"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T04:03:00Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14347-ND",+ "status": "found",+ "lifecycle": "Obsolete"+ },+ "mouser": {+ "pn": "595-PCI2050BPDV",+ "status": "found",+ "lifecycle": "Obsolete"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "2",+ "name": "S_REQ1",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 1; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "3",+ "name": "S_REQ2",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 2; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "4",+ "name": "S_REQ3",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 3; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "5",+ "name": "S_REQ4",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 4; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "6",+ "name": "S_REQ5",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 5; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "7",+ "name": "S_REQ6",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 6; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "8",+ "name": "S_REQ7",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 7; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "9",+ "name": "S_REQ8",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 8; the bridge internal arbiter uses it, and up to ten masters including the bridge can be on the secondary bus."+ },+ {+ "number": "10",+ "name": "S_GNT0",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "11",+ "name": "S_GNT1",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "13",+ "name": "S_GNT2",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "14",+ "name": "S_GNT3",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "15",+ "name": "S_GNT4",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "16",+ "name": "S_GNT5",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "17",+ "name": "S_GNT6",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "18",+ "name": "S_GNT7",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "19",+ "name": "S_GNT8",+ "type": "output",+ "description": "Secondary PCI bus grant output; function not stated in the provided excerpt (signal name from Table 2-1)."+ },+ {+ "number": "20",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "21",+ "name": "S_CLK",+ "type": "input",+ "description": "Secondary PCI bus clock input; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "22",+ "name": "S_RST",+ "type": "input",+ "description": "Secondary PCI bus reset; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "23",+ "name": "S_CFN",+ "type": "input",+ "description": "Secondary configuration-function signal; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "24",+ "name": "HS_SWITCH/GPIO3",+ "type": "input",+ "description": "General-purpose I/O 3; in cPCI mode it is HS_SWITCH, which provides the status of the ejector handle switch to the cPCI logic."+ },+ {+ "number": "25",+ "name": "GPIO2",+ "type": "bidirectional",+ "description": "General-purpose I/O terminal; no further detail given in the provided excerpt."+ },+ {+ "number": "26",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "27",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose I/O terminal; no further detail given in the provided excerpt."+ },+ {+ "number": "28",+ "name": "GPIO0",+ "type": "bidirectional",+ "description": "General-purpose I/O terminal; no further detail given in the provided excerpt."+ },+ {+ "number": "29",+ "name": "S_CLKOUT0",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "30",+ "name": "S_CLKOUT1",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "31",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "32",+ "name": "S_CLKOUT2",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "33",+ "name": "S_CLKOUT3",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "34",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "35",+ "name": "S_CLKOUT4",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "36",+ "name": "S_CLKOUT5",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "37",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "38",+ "name": "S_CLKOUT6",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "39",+ "name": "S_CLKOUT7",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "40",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "41",+ "name": "S_CLKOUT8",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "42",+ "name": "S_CLKOUT9",+ "type": "output",+ "description": "Secondary PCI bus clock output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "43",+ "name": "P_RST",+ "type": "input",+ "description": "Primary PCI bus reset; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "44",+ "name": "BPCCE",+ "type": "input",+ "description": "Bus/power clock control enable; when tied high and the device is in D3, the secondary clocks are disabled and driven to 0 to allow the secondary bus to enter B2, and when tied low D3 has no effect on secondary clocks."+ },+ {+ "number": "45",+ "name": "P_CLK",+ "type": "input",+ "description": "Primary PCI bus clock input; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "46",+ "name": "P_GNT",+ "type": "input",+ "description": "Primary PCI bus grant input; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "47",+ "name": "P_REQ",+ "type": "output",+ "description": "Primary PCI bus request output; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "48",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "49",+ "name": "P_AD31",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "50",+ "name": "P_AD30",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "51",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "52",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "53",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "54",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "55",+ "name": "P_AD29",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "56",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "57",+ "name": "P_AD28",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "58",+ "name": "P_AD27",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "59",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "60",+ "name": "P_AD26",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "61",+ "name": "P_AD25",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "62",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "63",+ "name": "P_AD24",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "64",+ "name": "P_C/BE3",+ "type": "bidirectional",+ "description": "Primary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "65",+ "name": "P_IDSEL",+ "type": "input",+ "description": "Primary PCI initialization device select; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "66",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "67",+ "name": "P_AD23",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "68",+ "name": "P_AD22",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "69",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "70",+ "name": "P_AD21",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "71",+ "name": "P_AD20",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "72",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "73",+ "name": "P_AD19",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "74",+ "name": "P_AD18",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "75",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "76",+ "name": "P_AD17",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "77",+ "name": "P_AD16",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "78",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "79",+ "name": "P_C/BE2",+ "type": "bidirectional",+ "description": "Primary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "80",+ "name": "P_FRAME",+ "type": "bidirectional",+ "description": "Primary PCI cycle frame; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "81",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "82",+ "name": "P_IRDY",+ "type": "bidirectional",+ "description": "Primary PCI initiator ready; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "83",+ "name": "P_TRDY",+ "type": "bidirectional",+ "description": "Primary PCI target ready; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "84",+ "name": "P_DEVSEL",+ "type": "bidirectional",+ "description": "Primary PCI device select; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "85",+ "name": "P_STOP",+ "type": "bidirectional",+ "description": "Primary PCI cycle stop; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "86",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "87",+ "name": "P_LOCK",+ "type": "bidirectional",+ "description": "Primary PCI bus lock; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "88",+ "name": "P_PERR",+ "type": "bidirectional",+ "description": "Primary PCI parity error indicator; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "89",+ "name": "P_SERR",+ "type": "bidirectional",+ "description": "Primary PCI system error; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "90",+ "name": "P_PAR",+ "type": "bidirectional",+ "description": "Primary PCI parity; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "91",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "92",+ "name": "P_C/BE1",+ "type": "bidirectional",+ "description": "Primary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "93",+ "name": "P_AD15",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "94",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "95",+ "name": "P_AD14",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "96",+ "name": "P_AD13",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "97",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "98",+ "name": "P_AD12",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "99",+ "name": "P_AD11",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "100",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "101",+ "name": "P_AD10",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "102",+ "name": "P_M66ENA",+ "type": "input",+ "description": "Primary interface 66 MHz enable, input-only; must be pulled low for 33-MHz primary operation (which forces the secondary bus to 33 MHz) and pulled high for 66-MHz operation."+ },+ {+ "number": "103",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "104",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "105",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "106",+ "name": "MS1",+ "type": "input",+ "description": "Mode select 1 input; the provided excerpt names the pin but does not give its detailed function."+ },+ {+ "number": "107",+ "name": "P_AD9",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "108",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "109",+ "name": "P_AD8",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "110",+ "name": "P_C/BE0",+ "type": "bidirectional",+ "description": "Primary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "111",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "112",+ "name": "P_AD7",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "113",+ "name": "P_AD6",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "114",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "115",+ "name": "P_AD5",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "116",+ "name": "P_AD4",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "117",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "118",+ "name": "P_AD3",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "119",+ "name": "P_AD2",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "120",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "121",+ "name": "P_AD1",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "122",+ "name": "P_AD0",+ "type": "bidirectional",+ "description": "Primary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "123",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "124",+ "name": "P_VCCP",+ "type": "power_in",+ "description": "Primary bus-signaling environment supply used in protection circuitry on primary bus I/O signals; TI recommends powering P_VCCP and S_VCCP up before VCC."+ },+ {+ "number": "125",+ "name": "CONFIG66",+ "type": "input",+ "description": "Input-only configuration of 66 MHz capability; tied high allows 66 MHz operation, tied low restricts the device to 33-MHz PCI operation."+ },+ {+ "number": "126",+ "name": "MSK_IN",+ "type": "input",+ "description": "Secondary clock mask input; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "127",+ "name": "HS_ENUM",+ "type": "output",+ "description": "Hot-swap ENUM output."+ },+ {+ "number": "128",+ "name": "HS_LED",+ "type": "output",+ "description": "Hot-swap LED output."+ },+ {+ "number": "129",+ "name": "TDI",+ "type": "input",+ "description": "JTAG serial data input; instructions and test data enter here and are sampled on the rising edge of TCK."+ },+ {+ "number": "130",+ "name": "TDO",+ "type": "output",+ "description": "JTAG serial data output through which test instructions and data leave the device."+ },+ {+ "number": "131",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "132",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select; causes state transitions in the test access port controller."+ },+ {+ "number": "133",+ "name": "TCK",+ "type": "input",+ "description": "JTAG boundary-scan clock that controls the JTAG logic."+ },+ {+ "number": "134",+ "name": "TRST",+ "type": "input",+ "description": "JTAG TAP reset; when asserted low it asynchronously forces the TAP controller into reset and initializes the test logic."+ },+ {+ "number": "135",+ "name": "S_VCCP",+ "type": "power_in",+ "description": "Secondary bus-signaling environment supply used in protection circuitry on secondary bus I/O signals; TI recommends powering S_VCCP up before VCC."+ },+ {+ "number": "136",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "137",+ "name": "S_AD0",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 0; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "138",+ "name": "S_AD1",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 1; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "139",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "140",+ "name": "S_AD2",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 2; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "141",+ "name": "S_AD3",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 3; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "142",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "143",+ "name": "S_AD4",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 4; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "144",+ "name": "S_AD5",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 5; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "145",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "146",+ "name": "S_AD6",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 6; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "147",+ "name": "S_AD7",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 7; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "148",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "149",+ "name": "S_C/BE0",+ "type": "bidirectional",+ "description": "Secondary PCI command/byte enable 0; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "150",+ "name": "S_AD8",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 8; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "151",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "152",+ "name": "S_AD9",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 9; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "153",+ "name": "S_M66ENA",+ "type": "bidirectional",+ "description": "Secondary 66 MHz enable, open-drain; driven low by the device when P_M66ENA is low, and when the primary bus runs at 66 MHz it must be pulled high for 66-MHz or low for 33-MHz secondary operation."+ },+ {+ "number": "154",+ "name": "S_AD10",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 10; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "155",+ "name": "MS0",+ "type": "input",+ "description": "Mode select 0 input; the provided excerpt names the pin but does not give its detailed function."+ },+ {+ "number": "156",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "157",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "158",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "159",+ "name": "S_AD11",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 11; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "160",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "161",+ "name": "S_AD12",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 12; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "162",+ "name": "S_AD13",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 13; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "163",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "164",+ "name": "S_AD14",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 14; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "165",+ "name": "S_AD15",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 15; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "166",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "167",+ "name": "S_C/BE1",+ "type": "bidirectional",+ "description": "Secondary PCI command/byte enable 1; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "168",+ "name": "S_PAR",+ "type": "bidirectional",+ "description": "Secondary parity; the bridge calculates even parity across S_AD and S_C/BE in all secondary read and write cycles, driving it one S_CLK later as master on writes."+ },+ {+ "number": "169",+ "name": "S_SERR",+ "type": "input",+ "description": "Secondary system error, passed through to the primary interface when enabled; the bridge never asserts it."+ },+ {+ "number": "170",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "171",+ "name": "S_PERR",+ "type": "bidirectional",+ "description": "Secondary parity error indicator, driven by a secondary device when calculated parity does not match S_PAR and it is enabled in the command register."+ },+ {+ "number": "172",+ "name": "S_LOCK",+ "type": "bidirectional",+ "description": "Secondary PCI bus lock used to lock the secondary bus and gain exclusive access as a master."+ },+ {+ "number": "173",+ "name": "S_STOP",+ "type": "bidirectional",+ "description": "Secondary cycle stop signal driven by a PCI target to request that the master stop the current transaction (used for target disconnects)."+ },+ {+ "number": "174",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "175",+ "name": "S_DEVSEL",+ "type": "bidirectional",+ "description": "Secondary device select; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "176",+ "name": "S_TRDY",+ "type": "bidirectional",+ "description": "Secondary target ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then."+ },+ {+ "number": "177",+ "name": "S_IRDY",+ "type": "bidirectional",+ "description": "Secondary initiator ready; a data phase completes on a rising S_CLK edge when S_IRDY and S_TRDY are both asserted, with wait states inserted until then."+ },+ {+ "number": "178",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "179",+ "name": "S_FRAME",+ "type": "bidirectional",+ "description": "Secondary cycle frame; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "180",+ "name": "S_C/BE2",+ "type": "bidirectional",+ "description": "Secondary PCI command/byte enable 2; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "181",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "182",+ "name": "S_AD16",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 16; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "183",+ "name": "S_AD17",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 17; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "184",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "185",+ "name": "S_AD18",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 18; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "186",+ "name": "S_AD19",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 19; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "187",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "188",+ "name": "S_AD20",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 20; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "189",+ "name": "S_AD21",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 21; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "190",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "191",+ "name": "S_AD22",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 22; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "192",+ "name": "S_AD23",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 23; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "193",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "194",+ "name": "S_C/BE3",+ "type": "bidirectional",+ "description": "Secondary PCI command/byte enable 3; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "195",+ "name": "S_AD24",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 24; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "196",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "197",+ "name": "S_AD25",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 25; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "198",+ "name": "S_AD26",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 26; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "199",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "200",+ "name": "S_AD27",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 27; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "201",+ "name": "S_AD28",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 28; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "202",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ },+ {+ "number": "203",+ "name": "S_AD29",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 29; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "204",+ "name": "S_AD30",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 30; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "205",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground terminal."+ },+ {+ "number": "206",+ "name": "S_AD31",+ "type": "bidirectional",+ "description": "Secondary PCI address/data bit 31; function not stated in the provided excerpt beyond the signal name."+ },+ {+ "number": "207",+ "name": "S_REQ0",+ "type": "input",+ "description": "Secondary PCI bus request input from secondary master 0; when the internal arbiter is disabled this pin is reconfigured as an external secondary bus grant for the bridge."+ },+ {+ "number": "208",+ "name": "VCC",+ "type": "power_in",+ "description": "Power-supply terminal for core logic (3.3 V)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package scope: the PDV pinout is taken from Table 2-1 and Figure 2-2 (208-terminal PDV LQFP). The 28; Lifecycle: the TI Package Option Addendum lists PCI2050BPDV as Obsolete (Call TI, 0 to 70 C). The PP; Excerpt gaps: pin functions and I/O types are given only for terminals in Tables 2-12 to 2-15 (pages"+ ],+ "pages_sent": 15,+ "cost_usd": 0.224,+ "at": "2026-10-08T04:02:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/pci2050b",+ "pages": 89,+ "sha256": "879d9875d1ecefb1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 208,+ "described": 208,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "pci2050bpdv.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 30,+ 30,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e3717f35ab17b7b1224af915b854103d4ab8675b952348f37773a9bee5c7a38e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "pci2050bpdv-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 30,+ 30,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "66c4ce99d80491daa7d0f05e25103ab1d325a308e4432d688c1c75e7f5958054",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}