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P25Q16SH-UXH-IR

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PUYA NOR FLASH, USON-8(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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P25Q16SH-UXH-IR

PUYA · NOR FLASH · USON-8(2x3)

P25Q16SH-UXH-IR from PUYA, in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip select input; the CS# notation denotes active-low selection.
2 SO bidirectional Serial data output for 1x I/O and serial data input and output for 4x I/O read mode.
3 WP# bidirectional Write protection input, active low, and serial data input and output for 4x I/O read mode; WP# and HOLD# functions are only available for Standard/Dual SPI.
4 GND power_in Ground of the device.
5 SI bidirectional Serial data input for 1x I/O and serial data input and output for 4x I/O read mode.
6 SCLK input Serial interface clock input.
7 HOLD#/RESET# bidirectional Hardware reset pin, active low, or pauses the device without deselecting it; also serial data input and output for 4x I/O read mode, and available only for Standard/Dual SPI.
8 VCC power_in Power supply of the device, specified for 2.3V to 3.6V.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer PUYA
Package USON-8(2x3)
Category Memory
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Single supply voltage VCC 2.3 3.6 V Read, erase and program 4
Operation temperature Ta -40 85 °C 8
Storage temperature -65 150 °C 8
Maximum operation voltage 4 V 8
Voltage on any pin with respect to ground -0.6 4.1 V 8
DC output current 5 mA 8
Output capacitance COUT 8 pF VOUT=GND 8
Input capacitance CIN 6 pF VIN=GND 8
Deep power down current IDPD 0.5 5 uA CS#=Vcc, all other inputs at 0V or Vcc 9
Read current (STR) at 85MHz ICC1 5 8 mA f=85MHz; IOUT=0mA 9
Read current (STR) at 120MHz ICC1 6 10 mA f=120MHz; IOUT=0mA 9
Read current (DTR) at 66MHz ICC2 5 8 mA f=66MHz; IOUT=0mA 9
Program current ICC3 3 4 mA CS#=Vcc 9
Erase current ICC4 3 4 mA CS#=Vcc 9
Input load current ILI 1 uA All inputs at CMOS level 9
Output leakage ILO 1 uA All inputs at CMOS level 9
Output low voltage VOL 0.2 V IOL=100uA 9
Clock frequency for standard instructions fSCLK 133 MHz 10
Clock frequency for READ instructions fRSCLK 55 MHz READ instructions 10
Clock frequency for 2READ, 4READ instructions fTSCLK 104 MHz 2READ, 4READ instructions 10
Clock frequency for DREAD, QREAD, C0H, QPI instructions fQ 133 MHz DREAD, QREAD, C0H, QPI 0Bh, QPI EBh, QPI 0Ch instructions 10
Clock frequency for WREAD instructions fQ 104 MHz WREAD instructions 10
Clock frequency for DTR instructions fD 66 MHz DTR instructions 10
Clock frequency for QPP fQPP 133 MHz QPP (Quad page program) 10
Clock high time tCH 3.3 ns 10
Clock low time tCL 3.3 ns 45% x (1fSCLK) 10
CS# active setup time tSLCH 5 ns Relative to SCLK 10
CS# not active hold time tCHSL 5 ns Relative to SCLK 10
Data in setup time tDVCH 2 ns 10
Data in hold time tCHDX 3 ns 10
CS# not active setup time tSHCH 5 ns Relative to SCLK 10
CS# deselect time from read to next read tSHSL 20 ns From Read to next Read 10
CS# deselect time from write, erase, program to read status register tSHSL 30 ns From Write, Erase, Program to Read Status Register 10
Output disable time tSHQZ 6 ns 10
Clock low to output valid tCLQV 7 ns Loading 30pF 10
Clock low to output valid tCLQV 6 ns Loading 15pF 10
Output hold time tCLQX 0 ns 10
HOLD# active setup time tHLCH 5 ns Relative to SCLK 10
HOLD# active hold time tCHHH 5 ns Relative to SCLK 10
HOLD# to output low-Z tHHQX 6 ns 10
HOLD# to output high-Z tHLQZ 6 ns 10
Write protect setup time tWHSL 20 ns 10
Write protect hold time tSHWL 100 ns 10
CS# high to deep power-down mode tDP 3 us 10
CS# high to standby mode without electronic signature read tRES1 8 us 10
CS# high to standby mode with electronic signature read tRES2 8 us 10
Write status register cycle time tW 8 12 ms 10
Load memory page data to buffer time (256 byte) tBL 60 us 256 byte 10
Buffer clear to next instruction latency tBC 200 ns 10
Erase suspend latency TESL 30 us 12
Program suspend latency TPSL 30 us 12
Latency between program resume and next suspend TPRS 20 us 12
Latency between erase resume and next suspend TERS 20 us 12
Page program time (up to 256 bytes) tPP 1.5 3 ms Up to 256 bytes 12
Page erase time tPE 16 30 ms 12
Sector erase time tSE 16 30 ms 12
Block erase time for 32K bytes tBE1 16 30 ms 32K bytes 12
Block erase time for 64K bytes tBE2 16 30 ms 64K bytes 12
Chip erase time tCE 130 180 ms 12
Standby current ISB 10 uA CS#, HOLD#, WP#=VIH all inputs at CMOS levels 9

CAD (KiCad official)

  • Symbol: P25Q16SH-UXH-IR
  • Footprint: Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm
  • 3D model: USON-8(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: p25q16sh-uxh-ir-etched.step / p25q16sh-uxh-ir-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); p25q16sh-uxh-ir.step / p25q16sh-uxh-ir.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: PUYA datasheet (109 pp, sha256 d5af0ef8b9726b7e, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF