# NTMD4840NR2G

**onsemi** · MOSFETs · SOIC-8

NTMD4840NR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of N-channel MOSFET 1; the datasheet gives no pin-specific limit, only device maximum ratings (VDSS 30 V, VGS ±20 V, TJ/TSTG −55 to +150 °C). |
| 2 | G1 | input | Gate of N-channel MOSFET 1; gate-to-source voltage is rated at ±20 V maximum. |
| 3 | S2 | passive | Source of N-channel MOSFET 2; the datasheet gives no pin-specific limit, only device maximum ratings (VDSS 30 V, VGS ±20 V, TJ/TSTG −55 to +150 °C). |
| 4 | G2 | input | Gate of N-channel MOSFET 2; gate-to-source voltage is rated at ±20 V maximum. |
| 5 | D2 | passive | Drain of N-channel MOSFET 2; pins 5 and 6 are both printed as DRAIN 2 and are connected together on the device, with the datasheet giving only device maximum ratings (VDSS 30 V, ID 7.5 A max). |
| 6 | D2 | passive | Drain of N-channel MOSFET 2; printed as DRAIN 2 together with pin 5, with the datasheet giving only device maximum ratings (VDSS 30 V, ID 7.5 A max). |
| 7 | D1 | passive | Drain of N-channel MOSFET 1; pins 7 and 8 are both printed as DRAIN 1 and are connected together on the device, with the datasheet giving only device maximum ratings (VDSS 30 V, ID 7.5 A max). |
| 8 | D1 | passive | Drain of N-channel MOSFET 1; printed as DRAIN 1 together with pin 7, with the datasheet giving only device maximum ratings (VDSS 30 V, ID 7.5 A max). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDSS |  |  | 30 | V |  | 1 |
| Gate-to-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Continuous Drain Current | ID |  |  | 5.5 | A | Steady state, TA = 25°C, Note 1 | 1 |
| Continuous Drain Current | ID |  |  | 4.4 | A | Steady state, TA = 70°C, Note 1 | 1 |
| Power Dissipation | PD |  |  | 1.14 | W | Steady state, TA = 25°C, Note 1 | 1 |
| Continuous Drain Current | ID |  |  | 4.5 | A | Steady state, TA = 25°C, Note 2 | 1 |
| Continuous Drain Current | ID |  |  | 3.5 | A | Steady state, TA = 70°C, Note 2 | 1 |
| Power Dissipation | PD |  |  | 0.68 | W | Steady state, TA = 25°C, Note 2 | 1 |
| Continuous Drain Current | ID |  |  | 7.5 | A | t < 10 s, TA = 25°C, Note 1 | 1 |
| Continuous Drain Current | ID |  |  | 6 | A | t < 10 s, TA = 70°C, Note 1 | 1 |
| Power Dissipation | PD |  |  | 1.95 | W | t < 10 s, TA = 25°C, Note 1 | 1 |
| Pulsed Drain Current | IDM |  |  | 30 | A | TA = 25°C, tp = 10 s | 1 |
| Operating Junction and Storage Temperature | TJ, TSTG | -55 |  | 150 | °C |  | 1 |
| Source Current (Body Diode) | IS |  |  | 2 | A |  | 1 |
| Single Pulse Drain-to-Source Avalanche Energy | EAS |  |  | 28 | mJ | TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 7.5 Apk, L = 1.0 mH, RG = 25 | 1 |
| Lead Temperature for Soldering Purposes | TL |  |  | 260 | °C | 1/8″ from case for 10 s | 1 |
| Junction-to-Ambient, Steady State | RJA |  |  | 110 | °C/W | Note 1 | 1 |
| Junction-to-Ambient, t ≤ 10 s | RJA |  |  | 64 | °C/W | Note 1 | 1 |
| Junction-to-Foot (Drain) | RJF |  |  | 40 | °C/W |  | 1 |
| Junction-to-Ambient, Steady State | RJA |  |  | 183.5 | °C/W | Note 2 | 1 |
| Drain-to-Source Breakdown Voltage | V(BR)DSS | 30 |  |  | V | VGS = 0 V, ID = 250 A | 2 |
| Zero Gate Voltage Drain Current, TJ = 25°C | IDSS |  |  | 1 | µA | VGS = 0 V, VDS = 24 V, TJ = 25°C | 2 |
| Zero Gate Voltage Drain Current, TJ = 100°C | IDSS |  |  | 10 | µA | VGS = 0 V, VDS = 24 V, TJ = 100°C | 2 |
| Gate-to-Source Leakage Current | IGSS | -100 |  | 100 | nA | VDS = 0 V, VGS = ±20 V | 2 |
| Gate Threshold Voltage | VGS(TH) | 1.5 |  | 3 | V | VGS = VDS, ID = 250 µA | 2 |
| Drain-to-Source On Resistance | RDS(on) |  | 16 | 24 | mΩ | VGS = 10 V, ID = 6.9 A | 2 |
| Drain-to-Source On Resistance | RDS(on) |  | 26 | 36 | mΩ | VGS = 4.5 V, ID = 5.0 A | 2 |
| Forward Diode Voltage, TJ = 25°C | VSD |  | 0.76 | 1 | V | VGS = 0 V, ID = 2.0 A, TJ = 25°C | 2 |
| Gate Resistance | RG |  | 2 | 3 | Ω |  | 2 |

## CAD (KiCad official)

- Symbol: `NTMD4840NR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ntmd4840nr2g-etched.step` / `ntmd4840nr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ntmd4840nr2g.step` / `ntmd4840nr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586187375239815168) (5 pp, sha256 `acab7f2f9ff66530`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ntmd4840nr2g-datasheet.pdf)