component
NSVMMUN2112LT1G
Public Made by Adomby adom
onsemi Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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NSVMMUN2112LT1G
onsemi · Digital Transistors · SOT-23
NSVMMUN2112LT1G from onsemi, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base is the input pin of the bias resistor transistor, with the datasheet stating a maximum input forward voltage VIN(fwd) of 40 Vdc and a maximum input reverse voltage VIN(rev) of 10 Vdc. |
| 2 | EMITTER | power_in | Emitter is the ground reference pin of the transistor (labeled GROUND in the datasheet), and the datasheet gives no separate electrical limit for it. |
| 3 | COLLECTOR | output | Collector is the output pin, with the datasheet stating a maximum collector-base voltage VCBO of 50 Vdc, a maximum collector-emitter voltage VCEO of 50 Vdc, and a continuous collector current IC of 100 mAdc. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector−Base Cutoff Current | ICBO | 100 | nAdc | VCB = 50 V, IE = 0 | 4 | ||
| Collector−Emitter Cutoff Current | ICEO | 500 | nAdc | VCE = 50 V, IB = 0 | 4 | ||
| Emitter−Base Cutoff Current | IEBO | 0.2 | mAdc | VEB = 6.0 V, IC = 0 | 4 | ||
| Collector−Base Breakdown Voltage | V(BR)CBO | 50 | Vdc | IC = 10 A, IE = 0 | 4 | ||
| Collector−Emitter Breakdown Voltage | V(BR)CEO | 50 | Vdc | IC = 2.0 mA, IB = 0 (Note 5: pulsed) | 4 | ||
| DC Current Gain | hFE | 60 | 100 | IC = 5.0 mA, VCE = 10 V (Note 5: pulsed) | 4 | ||
| Collector−Emitter Saturation Voltage | VCE(sat) | 0.25 | Vdc | IC = 10 mA, IB = 0.3 mA (Note 5: pulsed) | 4 | ||
| Input Voltage (off) | Vi(off) | 1.2 | 0.8 | Vdc | VCE = 5.0 V, IC = 100 A | 4 | |
| Input Voltage (on) | Vi(on) | 2.5 | 1.7 | Vdc | VCE = 0.3 V, IC = 5.0 mA | 4 | |
| Output Voltage (on) | VOL | 0.2 | Vdc | VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k | 4 | ||
| Output Voltage (off) | VOH | 4.9 | Vdc | VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k | 4 | ||
| Input Resistor R1 | R1 | 15.4 | 22 | 28.6 | k | 4 | |
| Resistor Ratio R1/R2 | R1/R2 | 0.8 | 1 | 1.2 | 4 | ||
| Collector−Base Voltage | VCBO | 50 | Vdc | TA = 25°C | 1 | ||
| Collector−Emitter Voltage | VCEO | 50 | Vdc | TA = 25°C | 1 | ||
| Collector Current − Continuous | IC | 100 | mAdc | TA = 25°C | 1 | ||
| Input Forward Voltage | VIN(fwd) | 40 | Vdc | TA = 25°C | 1 | ||
| Input Reverse Voltage | VIN(rev) | 10 | Vdc | TA = 25°C | 1 | ||
| Total Device Dissipation | PD | 246 | mW | TA = 25°C (Note 1: FR-4 @ Minimum Pad) | 3 | ||
| Total Device Dissipation | PD | 400 | mW | TA = 25°C (Note 2: FR-4 @ 1.0 x 1.0 Inch Pad) | 3 | ||
| Derate above 25°C | 2 | mW/°C | Note 1: FR-4 @ Minimum Pad | 3 | |||
| Derate above 25°C | 3.2 | mW/°C | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 | |||
| Thermal Resistance, Junction to Ambient | RJA | 508 | °C/W | Note 1: FR-4 @ Minimum Pad | 3 | ||
| Thermal Resistance, Junction to Ambient | RJA | 311 | °C/W | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 | ||
| Thermal Resistance, Junction to Lead | RJL | 174 | °C/W | Note 1: FR-4 @ Minimum Pad | 3 | ||
| Thermal Resistance, Junction to Lead | RJL | 208 | °C/W | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 | ||
| Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 3 | ||
| Input Resistor R2 (nominal, title) | R2 | 22 | k | 1 |
CAD (KiCad official)
- Symbol:
NSVMMUN2112LT1G - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
nsvmmun2112lt1g-etched.step/nsvmmun2112lt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsvmmun2112lt1g.step/nsvmmun2112lt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (13 pp, sha256
90e0311802ee1b16, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# NSVMMUN2112LT1G
**onsemi** · Digital Transistors · SOT-23
NSVMMUN2112LT1G from onsemi, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BASE | input | Base is the input pin of the bias resistor transistor, with the datasheet stating a maximum input forward voltage VIN(fwd) of 40 Vdc and a maximum input reverse voltage VIN(rev) of 10 Vdc. |
| 2 | EMITTER | power_in | Emitter is the ground reference pin of the transistor (labeled GROUND in the datasheet), and the datasheet gives no separate electrical limit for it. |
| 3 | COLLECTOR | output | Collector is the output pin, with the datasheet stating a maximum collector-base voltage VCBO of 50 Vdc, a maximum collector-emitter voltage VCEO of 50 Vdc, and a continuous collector current IC of 100 mAdc. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector−Base Cutoff Current | ICBO | | | 100 | nAdc | VCB = 50 V, IE = 0 | 4 |
| Collector−Emitter Cutoff Current | ICEO | | | 500 | nAdc | VCE = 50 V, IB = 0 | 4 |
| Emitter−Base Cutoff Current | IEBO | | | 0.2 | mAdc | VEB = 6.0 V, IC = 0 | 4 |
| Collector−Base Breakdown Voltage | V(BR)CBO | 50 | | | Vdc | IC = 10 A, IE = 0 | 4 |
| Collector−Emitter Breakdown Voltage | V(BR)CEO | 50 | | | Vdc | IC = 2.0 mA, IB = 0 (Note 5: pulsed) | 4 |
| DC Current Gain | hFE | 60 | 100 | | | IC = 5.0 mA, VCE = 10 V (Note 5: pulsed) | 4 |
| Collector−Emitter Saturation Voltage | VCE(sat) | | | 0.25 | Vdc | IC = 10 mA, IB = 0.3 mA (Note 5: pulsed) | 4 |
| Input Voltage (off) | Vi(off) | | 1.2 | 0.8 | Vdc | VCE = 5.0 V, IC = 100 A | 4 |
| Input Voltage (on) | Vi(on) | 2.5 | 1.7 | | Vdc | VCE = 0.3 V, IC = 5.0 mA | 4 |
| Output Voltage (on) | VOL | | | 0.2 | Vdc | VCC = 5.0 V, VB = 2.5 V, RL = 1.0 k | 4 |
| Output Voltage (off) | VOH | 4.9 | | | Vdc | VCC = 5.0 V, VB = 0.5 V, RL = 1.0 k | 4 |
| Input Resistor R1 | R1 | 15.4 | 22 | 28.6 | k | | 4 |
| Resistor Ratio R1/R2 | R1/R2 | 0.8 | 1 | 1.2 | | | 4 |
| Collector−Base Voltage | VCBO | | | 50 | Vdc | TA = 25°C | 1 |
| Collector−Emitter Voltage | VCEO | | | 50 | Vdc | TA = 25°C | 1 |
| Collector Current − Continuous | IC | | | 100 | mAdc | TA = 25°C | 1 |
| Input Forward Voltage | VIN(fwd) | | | 40 | Vdc | TA = 25°C | 1 |
| Input Reverse Voltage | VIN(rev) | | | 10 | Vdc | TA = 25°C | 1 |
| Total Device Dissipation | PD | | | 246 | mW | TA = 25°C (Note 1: FR-4 @ Minimum Pad) | 3 |
| Total Device Dissipation | PD | | | 400 | mW | TA = 25°C (Note 2: FR-4 @ 1.0 x 1.0 Inch Pad) | 3 |
| Derate above 25°C | | | | 2 | mW/°C | Note 1: FR-4 @ Minimum Pad | 3 |
| Derate above 25°C | | | | 3.2 | mW/°C | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 |
| Thermal Resistance, Junction to Ambient | RJA | | | 508 | °C/W | Note 1: FR-4 @ Minimum Pad | 3 |
| Thermal Resistance, Junction to Ambient | RJA | | | 311 | °C/W | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 |
| Thermal Resistance, Junction to Lead | RJL | | | 174 | °C/W | Note 1: FR-4 @ Minimum Pad | 3 |
| Thermal Resistance, Junction to Lead | RJL | | | 208 | °C/W | Note 2: FR-4 @ 1.0 x 1.0 Inch Pad | 3 |
| Junction and Storage Temperature Range | TJ, Tstg | -55 | | 150 | °C | | 3 |
| Input Resistor R2 (nominal, title) | R2 | | 22 | | k | | 1 |
## CAD (KiCad official)
- Symbol: `NSVMMUN2112LT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `nsvmmun2112lt1g-etched.step` / `nsvmmun2112lt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `nsvmmun2112lt1g.step` / `nsvmmun2112lt1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589983324719644672) (13 pp, sha256 `90e0311802ee1b16`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/nsvmmun2112lt1g-datasheet.pdf)