NSS40301MDR2G

{
  "slug": "nss40301mdr2g",
  "version": "0.1.0",
  "type": "component",
  "description": "onsemi Bipolar (BJT), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "transistors-thyristors",
    "nss40301mdr2g",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "nss40301mdr2g.kicad_sym",
    "nss40301mdr2g.kicad_mod",
    "nss40301mdr2g.glb",
    "nss40301mdr2g.step",
    "nss40301mdr2g.lbr",
    "docs/hero.png",
    "docs/nss40301mdr2g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "nss40301mdr2g-hero.glb",
    "nss40301mdr2g-hero.overlay.json",
    "nss40301mdr2g-etched.glb"
  ],
  "component": {
    "mpn": "NSS40301MDR2G",
    "manufacturer": "onsemi",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Transistors/Thyristors",
    "subcategory": "Bipolar (BJT)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929576034570240",
    "parts": {
      "symbol": "nss40301mdr2g.kicad_sym",
      "footprint": "nss40301mdr2g.kicad_mod",
      "model_3d": "nss40301mdr2g-hero.glb",
      "model_3d_plain": "nss40301mdr2g-etched.glb",
      "model_3d_step": "nss40301mdr2g-etched.step",
      "model_3d_step_plain": "nss40301mdr2g.step",
      "lbr": "nss40301mdr2g.lbr"
    },
    "distributor_links": {
      "lcsc": "C905020",
      "digikey": "NSS40301MDR2GOSTR-ND",
      "mouser": "863-NSS40301MDR2G"
    },
    "distributor_check": {
      "checked_at": "2026-10-19T04:54:06Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "NSS40301MDR2GOSTR-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "863-NSS40301MDR2G",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "E1",
        "type": "passive",
        "description": "Emitter of NPN die #1 (Style 16 pinout); transistor rated VCEO 40 V, IC 3.0 A continuous."
      },
      {
        "number": "2",
        "name": "B1",
        "type": "input",
        "description": "Base of NPN die #1 (Style 16 pinout); VEBO max 6.0 Vdc."
      },
      {
        "number": "3",
        "name": "E2",
        "type": "passive",
        "description": "Emitter of NPN die #2 (Style 16 pinout); transistor rated VCEO 40 V, IC 3.0 A continuous."
      },
      {
        "number": "4",
        "name": "B2",
        "type": "input",
        "description": "Base of NPN die #2 (Style 16 pinout); VEBO max 6.0 Vdc."
      },
      {
        "number": "5",
        "name": "C2",
        "type": "passive",
        "description": "Collector of NPN die #2, tied with pin 6 (Style 16 pinout); VCEO 40 V, IC 3.0 A continuous, 6.0 A peak."
      },
      {
        "number": "6",
        "name": "C2",
        "type": "passive",
        "description": "Collector of NPN die #2, tied with pin 5 (Style 16 pinout); VCEO 40 V, IC 3.0 A continuous, 6.0 A peak."
      },
      {
        "number": "7",
        "name": "C1",
        "type": "passive",
        "description": "Collector of NPN die #1, tied with pin 8 (Style 16 pinout); VCEO 40 V, IC 3.0 A continuous, 6.0 A peak."
      },
      {
        "number": "8",
        "name": "C1",
        "type": "passive",
        "description": "Collector of NPN die #1, tied with pin 7 (Style 16 pinout); VCEO 40 V, IC 3.0 A continuous, 6.0 A peak."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin assignments are taken from the Style 16 diagram on page 7; page 1 confirms the NSS40301MDR2G mar; The datasheet gives no per-pin electrical limits. Pin types are set to passive for the transistor te; Pins 5/6 and 7/8 are the same net within each die and are printed as paired collector pins; the data"
        ],
        "pages_sent": 8,
        "cost_usd": 0.0535,
        "at": "2026-10-19T04:53:52"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588929576034570240",
        "pages": 8,
        "sha256": "3539b8f545a7f7e7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
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        "file": "nss40301mdr2g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "nss40301mdr2g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "22ff27a8ddc31294941f925df5e8e8ac91c7dc026a6e2aa99cf48dbc97269ec2",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  }
}