component

NSMC05S60B0

Public Made by Adom

by adom

WXNSIC Intelligent Power Modules (IPM), SOP-23. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsnsmc05s60b0
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs nsmc05s60b0: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers nsmc05s60b0: viewers · Ray 1mo ago
nsmc05s60b0-etched.fit.json nsmc05s60b0: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
nsmc05s60b0-etched.glb nsmc05s60b0: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
nsmc05s60b0-etched.step nsmc05s60b0: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
nsmc05s60b0.glb Publish 0.1.0 · Ray 1mo ago
nsmc05s60b0.kicad_mod Publish 0.1.0 · Ray 1mo ago
nsmc05s60b0.kicad_sym Publish 0.1.0 · Ray 1mo ago
nsmc05s60b0.lbr Publish 0.1.0 · Ray 1mo ago
nsmc05s60b0.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.1.0 · Ray 1mo ago
page.json nsmc05s60b0: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md nsmc05s60b0: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

NSMC05S60B0

WXNSIC · Intelligent Power Modules (IPM) · SOP-23

NSMC05S60B0 from WXNSIC, in a SOP-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 COM power_in IC common supply ground. Reference for VCC and logic input signals.
2 VB(U) power_in Bootstrap/bias voltage for U-phase high-side IGBT gate driver. Referenced to VS(U); operating range 12-18.5V, absolute max 20V between VB and VS.
3 VCC(U) power_in Bias supply for U-phase HVIC and low-side IGBT gate driver. Operating range 12-18.5V referenced to COM; absolute max 20V.
4 IN(UH) input U-phase high-side PWM signal input. Active-high logic compatible with 3.3V/5V MCU; VIH >= 2.5V, VIL <= 0.8V; typical ON threshold 3.0V.
5 IN(UL) input U-phase low-side PWM signal input. Active-high logic compatible with 3.3V/5V MCU; VIH >= 2.5V, VIL <= 0.8V.
6 N.C unconnected No connection. Leave floating.
7 VB(V) power_in Bootstrap/bias voltage for V-phase high-side IGBT gate driver. Referenced to VS(V); operating range 12-18.5V, absolute max 20V.
8 VCC(V) power_in Bias supply for V-phase HVIC and low-side IGBT gate driver. 12-18.5V referenced to COM; absolute max 20V.
9 IN(VH) input V-phase high-side PWM signal input. Active-high 3.3V/5V logic compatible; VIH >= 2.5V, VIL <= 0.8V.
10 IN(VL) input V-phase low-side PWM signal input. Active-high 3.3V/5V logic compatible; VIH >= 2.5V, VIL <= 0.8V.
11 N.C unconnected No connection. Leave floating.
12 VB(W) power_in Bootstrap/bias voltage for W-phase high-side IGBT gate driver. Referenced to VS(W); operating range 12-18.5V, absolute max 20V.
13 VCC(W) power_in Bias supply for W-phase HVIC and low-side IGBT gate driver. 12-18.5V referenced to COM; absolute max 20V.
14 IN(WH) input W-phase high-side PWM signal input. Active-high 3.3V/5V logic compatible; VIH >= 2.5V, VIL <= 0.8V.
15 IN(WL) input W-phase low-side PWM signal input. Active-high 3.3V/5V logic compatible; VIH >= 2.5V, VIL <= 0.8V.
16 N.C unconnected No connection. Leave floating.
17 P power_in Positive DC-link input. Common collector of the three high-side IGBTs. Typical 300V, max 400V bus.
18 U/VS(U) output U-phase inverter output to motor and high-side driver VS reference for U phase. Handles up to 5A continuous / 15A peak IGBT current.
19 NU power_in Negative DC-link input for U-phase (independent low-side emitter). Connect to shunt resistor for per-phase current sensing.
20 NV power_in Negative DC-link input for V-phase (independent low-side emitter). Connect to shunt resistor for per-phase current sensing.
21 V/VS(V) output V-phase inverter output to motor and high-side driver VS reference for V phase. Handles up to 5A continuous / 15A peak.
22 NW power_in Negative DC-link input for W-phase (independent low-side emitter). Connect to shunt resistor for per-phase current sensing.
23 W/VS(W) output W-phase inverter output to motor and high-side driver VS reference for W phase. Handles up to 5A continuous / 15A peak.

Key specifications

Parameter Value
Manufacturer WXNSIC
Package SOP-23
Category Transistors/Thyristors
Pins 23

Ordering variants

Same part, different packaging or reel option.

  • NSMC05S60B0

CAD (KiCad official)

  • Symbol: NSMC05S60B0
  • Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
  • 3D model: SOP-23 (KiCad packages3D, STEP)
  • 3D model files: nsmc05s60b0-etched.step / nsmc05s60b0-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nsmc05s60b0.step / nsmc05s60b0.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WXNSIC datasheet (8 pp, sha256 283bd4730e2c4a43, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF