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NSI8021N1-DSPR
Public Made by Adomby adom
NOVOSENSE Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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Contents
README
markdownNSI8021N1-DSPR
NOVOSENSE · Digital Isolators · SOIC-8
NSI8021N1-DSPR from NOVOSENSE, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Power supply for isolator side 1, operating from 2.5 V to 5.5 V, with a 0.1 µF bypass capacitor required between VDD1 and GND1 placed as close to the package as possible. |
| 2 | OUTA | output | Logic output A, with absolute maximum output voltage of -0.4 V to VDD+0.4 V (not to exceed 6.5 V) and output current rated at ±15 mA. |
| 3 | INB | input | Logic input B, with absolute maximum input voltage of -0.4 V to VDD+0.4 V (not to exceed 6.5 V). |
| 4 | GND1 | power_in | Ground 1, the ground reference for isolator side 1. |
| 5 | GND2 | power_in | Ground 2, the ground reference for isolator side 2. |
| 6 | OUTB | output | Logic output B, with absolute maximum output voltage of -0.4 V to VDD+0.4 V (not to exceed 6.5 V) and output current rated at ±15 mA. |
| 7 | INA | input | Logic input A, with absolute maximum input voltage of -0.4 V to VDD+0.4 V (not to exceed 6.5 V). |
| 8 | VDD2 | power_in | Power supply for isolator side 2, operating from 2.5 V to 5.5 V, with a 0.1 µF bypass capacitor required between VDD2 and GND2 placed as close to the package as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NOVOSENSE |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power Supply Voltage | VDD1, VDD2 | -0.5 | 6.5 | V | 3 | ||
| Power Supply Voltage (recommended operating range) | VDD1, VDD2 | 2.5 | 5.5 | V | Ta=-40℃ to 125℃ | 3 | |
| Maximum Input Voltage | VINA, VINB | -0.4 | V | 3 | |||
| Maximum Output Voltage | VOUTA, VOUTB | -0.4 | V | 3 | |||
| Maximum Input/Output Pulse Voltage | VINA, VINB, VOUTA, VOUTB | -0.8 | V | Pulse width less than 100ns, duty cycle less than 10% | 3 | ||
| Common-Mode Transients | CMTI | -100 | 100 | kV/us | 3 | ||
| Output current | Io | -15 | 15 | mA | 3 | ||
| Maximum Surge Isolation Voltage | VIOSM | 5.3 | kV | 3 | |||
| Operating Temperature | Topr | -40 | 125 | ℃ | 3 | ||
| Storage Temperature | Tstg | -40 | 150 | ℃ | 3 | ||
| Electrostatic discharge HBM | HBM | -4000 | 4000 | V | 3 | ||
| Electrostatic discharge CDM | CDM | -2000 | 2000 | V | 3 | ||
| Input Pull high or low Current | Ipull | 8 | 15 | uA | VDD1, VDD2 = 2.5V~5.5V | 3 | |
| Common Mode Transient Immunity | CMTI | -80 | 100 | 80 | kV/us | 4 | |
| Data Rate | DR | 0 | 10 | Mbps | VDD1=VDD2=5V±10%, Ta=-40℃ to 125℃ | 4 | |
| Output impedance tolerance (typical 50 ohm) | Rout | -40 | 40 | % | Typical output impedance of isolator driver channel, approximately 50 ohm | 10 | |
| Case Temperature | Ts | 150 | ℃ | DIN VDE V 0884-11 insulation characteristics | 8 | ||
| Power on Reset threshold | VDDPOR | 2.2 | V | POR threshold as during power-up | 3 | ||
| POR threshold Hysteresis | VDD HYS | 0.1 | V | POR threshold Hysteresis | 3 | ||
| Low Level Output Voltage | VOL | 0.3 | V | IOL ≤ 4mA | 3 | ||
| Output Impedance | Rout | 50 | ohm | 3 | |||
| Start Up Time after POR | trbs | 40 | usec | 4 | |||
| Supply current IDD1(Q0) | IDD1(Q0) | 0.8 | mA | VDD1=VDD2=5V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 4 | ||
| Supply current IDD2(Q0) | IDD2(Q0) | 0.8 | mA | VDD1=VDD2=5V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 4 | ||
| Supply current IDD1(Q1) | IDD1(Q1) | 1.4 | mA | VDD1=VDD2=5V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 4 | ||
| Supply current IDD2(Q1) | IDD2(Q1) | 1.4 | mA | VDD1=VDD2=5V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 4 | ||
| Supply current IDD1(0.5M) | IDD1(0.5M) | 1.25 | mA | VDD1=VDD2=5V±10%; All Input with 500kbps, CL=15pF | 4 | ||
| Supply current IDD2(0.5M) | IDD2(0.5M) | 1.25 | mA | VDD1=VDD2=5V±10%; All Input with 500kbps, CL=15pF | 4 | ||
| Minimum Pulse Width | PW | 50 | ns | VDD1=VDD2=5V±10%, Ta=-40℃ to 125℃ | 4 | ||
| Propagation Delay tPLH | tPLH | 30 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=5V±10% | 4 | ||
| Propagation Delay tPHL | tPHL | 30 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=5V±10% | 4 | ||
| Pulse Width Distortion /tPHL, tPLH/ | PWD | 10 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=5V±10% | 4 | ||
| Rising Time | tr | 5 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=5V±10% | 4 | ||
| Falling Time | tf | 5 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=5V±10% | 4 | ||
| Peak Eye Diagram Jitter | tJIT(PK) | 350 | ps | VDD1=VDD2=5V±10% | 4 | ||
| Channel-to-Channel Delay Skew | tSK(c2c) | 10 | ns | VDD1=VDD2=5V±10% | 4 | ||
| Part-to-Part Delay Skew | tSK(p2p) | 10 | ns | VDD1=VDD2=5V±10% | 4 | ||
| Supply current IDD1(Q0) | IDD1(Q0) | 0.77 | mA | VDD1=VDD2=3.3V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 5 | ||
| Supply current IDD2(Q0) | IDD2(Q0) | 0.77 | mA | VDD1=VDD2=3.3V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 5 | ||
| Supply current IDD1(Q1) | IDD1(Q1) | 1.35 | mA | VDD1=VDD2=3.3V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 5 | ||
| Supply current IDD2(Q1) | IDD2(Q1) | 1.35 | mA | VDD1=VDD2=3.3V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 5 | ||
| Supply current IDD1(0.5M) | IDD1(0.5M) | 1.11 | mA | VDD1=VDD2=3.3V±10%; All Input with 500kbps, CL = 15pF | 5 | ||
| Supply current IDD2(0.5M) | IDD2(0.5M) | 1.11 | mA | VDD1=VDD2=3.3V±10%; All Input with 500kbps, CL = 15pF | 5 | ||
| Propagation Delay tPLH | tPLH | 30 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=3.3V±10% | 5 | ||
| Propagation Delay tPHL | tPHL | 30 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=3.3V±10% | 5 | ||
| Pulse Width Distortion /tPHL, tPLH/ | PWD | 10 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=3.3V±10% | 5 | ||
| Part-to-Part Delay Skew | tSK(p2p) | 10 | ns | VDD1=VDD2=3.3V±10% | 5 | ||
| Supply current IDD1(Q0) | IDD1(Q0) | 0.75 | mA | VDD1=VDD2=2.5V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 6 | ||
| Supply current IDD2(Q0) | IDD2(Q0) | 0.75 | mA | VDD1=VDD2=2.5V±10%; All Input 0V for NSI8021x0 Or All Input at supply for NSI8021x1 | 6 | ||
| Supply current IDD1(Q1) | IDD1(Q1) | 1.33 | mA | VDD1=VDD2=2.5V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 6 | ||
| Supply current IDD2(Q1) | IDD2(Q1) | 1.33 | mA | VDD1=VDD2=2.5V±10%; All Input at supply for NSI8021x0 Or All Input 0V for NSI8021x1 | 6 | ||
| Supply current IDD1(0.5M) | IDD1(0.5M) | 1.08 | mA | VDD1=VDD2=2.5V±10%; All Input with 500kbps, CL = 15pF | 6 | ||
| Supply current IDD2(0.5M) | IDD2(0.5M) | 1.08 | mA | VDD1=VDD2=2.5V±10%; All Input with 500kbps, CL = 15pF | 6 | ||
| Minimum Pulse Width | PW | 50 | ns | VDD1=VDD2=2.5V±10% | 6 | ||
| Propagation Delay tPLH | tPLH | 440 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=2.5V±10% | 6 | ||
| Propagation Delay tPHL | tPHL | 440 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=2.5V±10% | 6 | ||
| Pulse Width Distortion /tPHL, tPLH/ | PWD | 10 | ns | See Figure 2.7, CL = 15pF; VDD1=VDD2=2.5V±10% | 6 | ||
| Part-to-Part Delay Skew | tSK(p2p) | 5 | ns | VDD1=VDD2=2.5V±10% | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN VDE V 0884-11, each NSI8020N/NSI8021N is proof tested by applying an insulation test voltage ≥ 847 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking bra | 9 |
CAD (KiCad official)
- Symbol:
NSI8021N1-DSPR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
nsi8021n1-dspr-etched.step/nsi8021n1-dspr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);nsi8021n1-dspr.step/nsi8021n1-dspr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NOVOSENSE datasheet (14 pp, sha256
b574019b05ce7a98, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).