component
NSG0462UQ
Public Made by Adomby adom
WXNSIC(国硅集成) Gate Drivers, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "NSG0462UQ",
"manufacturer": "WXNSIC(国硅集成)",
"package": "QFN-16-EP(3x3)",
"pin_count": 17,
"category": "Motor Driver ICs",
"subcategory": "Gate Drivers",
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"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "quota"
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"pins": [
{
"number": "1",
"name": "HIN1",
"type": "input",
"description": "Phase 1 high-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "2",
"name": "LIN3",
"type": "input",
"description": "Phase 3 low-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "3",
"name": "LIN2",
"type": "input",
"description": "Phase 2 low-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "4",
"name": "LIN1",
"type": "input",
"description": "Phase 1 low-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "5",
"name": "LDO5",
"type": "power_out",
"description": "5 V LDO output for powering an MCU or other devices, 4.7 V to 5.3 V, up to 40 mA (VCC 10 V to 28 V) or 50 mA (VCC 11 V to 28 V), absolute max 6 V."
},
{
"number": "6",
"name": "VCC1",
"type": "power_in",
"description": "Supply voltage pin 1 for the driver, recommended 5 V to 28 V, absolute max 40 V, referenced to GND."
},
{
"number": "7",
"name": "VCC2",
"type": "power_in",
"description": "Supply voltage pin 2 for the driver, recommended 5 V to 28 V, absolute max 40 V, referenced to GND."
},
{
"number": "8",
"name": "HO1",
"type": "output",
"description": "Phase 1 high-side gate drive output, with VHO between VCC-15 V and VCC, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "9",
"name": "LO1",
"type": "output",
"description": "Phase 1 low-side gate drive output, with high level 8.5 V to 11.5 V (10 V typ), absolute max 15 V, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "10",
"name": "HO2",
"type": "output",
"description": "Phase 2 high-side gate drive output, with VHO between VCC-15 V and VCC, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "11",
"name": "LO2",
"type": "output",
"description": "Phase 2 low-side gate drive output, with high level 8.5 V to 11.5 V (10 V typ), absolute max 15 V, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "12",
"name": "HO3",
"type": "output",
"description": "Phase 3 high-side gate drive output, with VHO between VCC-15 V and VCC, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "13",
"name": "LO3",
"type": "output",
"description": "Phase 3 low-side gate drive output, with high level 8.5 V to 11.5 V (10 V typ), absolute max 15 V, and short-circuit pulse currents of 50 mA source and 300 mA sink."
},
{
"number": "14",
"name": "GND",
"type": "power_in",
"description": "Chip ground reference; all voltage parameters in the datasheet are referenced to this pin."
},
{
"number": "15",
"name": "HIN3",
"type": "input",
"description": "Phase 3 high-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "16",
"name": "HIN2",
"type": "input",
"description": "Phase 2 high-side logic input with ON threshold min 2.9 V, OFF threshold max 0.4 V, and absolute range -0.3 V to 26 V."
},
{
"number": "17",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet gives only the QFN16 (3 mm x 3 mm) package and a 16-pin table. The package hint says Q; Pin order is taken from the printed Table 6-1 (Figure 6-1 top view is an image and was not readable ; Absolute maximum for HIN/LIN is listed in the table under the label '逻辑输出' (logic output), which app",
"exposed pad 17 added from the footprint"
],
"pages_sent": 9,
"cost_usd": 0.044,
"at": "2026-10-17T13:43:41"
},
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"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604436514676101120",
"pages": 9,
"sha256": "525eb908bd516dc1",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
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