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NLV74HC138ADR2G

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onsemi Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NLV74HC138ADR2G

onsemi · Signal Switches, Multiplexers, Decoders · SOIC-16

NLV74HC138ADR2G from onsemi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address input; when the chip is selected, the A0-A2 combination determines which one of the eight active-low outputs is asserted, and unused inputs must be tied to GND or VCC.
2 A1 input Address input; when the chip is selected, the A0-A2 combination determines which one of the eight active-low outputs is asserted, and unused inputs must be tied to GND or VCC.
3 A2 input Address input; when the chip is selected, the A0-A2 combination determines which one of the eight active-low outputs is asserted, and unused inputs must be tied to GND or VCC.
4 CS2 input Active-low chip select; the chip is selected only when CS2 and CS3 are low and CS1 is high, otherwise all outputs are held high.
5 CS3 input Active-low chip select; the chip is selected only when CS2 and CS3 are low and CS1 is high, otherwise all outputs are held high.
6 CS1 input Active-high chip select; the chip is selected only when CS1 is high and CS2 and CS3 are low, otherwise all outputs are held high.
7 Y7 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
8 GND power_in Ground reference for all voltages; input and output voltages are specified relative to GND.
9 Y6 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
10 Y5 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
11 Y4 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
12 Y3 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
13 Y2 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
14 Y1 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
15 Y0 output Active-low decoded output that goes low when addressed with the chip selected and stays high otherwise.
16 VCC power_in Positive supply; recommended operating range is 2.0 V to 6.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage (Referenced to GND) VCC -0.5 7 V Referenced to GND 3
DC Input Voltage (Referenced to GND) Vin -0.5 V Referenced to GND; upper limit printed as VCC + 0.5 V 3
DC Output Voltage (Referenced to GND) Vout -0.5 V Referenced to GND; upper limit printed as VCC + 0.5 V 3
DC Input Current, per Pin Iin -20 20 mA per pin 3
DC Output Current, per Pin Iout -25 25 mA per pin 3
DC Supply Current, VCC and GND Pins ICC -50 50 mA VCC and GND pins 3
Power Dissipation in Still Air, SOIC Package PD 500 mW SOIC package, still air 3
Storage Temperature Tstg -65 150 °C 3
Lead Temperature TL 260 °C 1 mm from case for 10 seconds (Plastic DIP, SOIC or TSSOP package) 3
DC Supply Voltage (Referenced to GND) VCC 2 6 V Referenced to GND 3
DC Input Voltage, Output Voltage (Referenced to GND) Vin, Vout 0 V Referenced to GND; upper limit printed as VCC 3
Operating Temperature, All Package Types TA -55 125 °C 3
Input Rise and Fall Time tr, tf 0 1000 ns VCC = 2.0 V (Figure 2) 3
Input Rise and Fall Time tr, tf 0 500 ns VCC = 4.5 V (Figure 2) 3
Input Rise and Fall Time tr, tf 0 400 ns VCC = 6.0 V (Figure 2) 3
Minimum High-Level Input Voltage VIH 1.5 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V 4
Minimum High-Level Input Voltage VIH 2.1 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V 4
Minimum High-Level Input Voltage VIH 3.15 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V 4
Minimum High-Level Input Voltage VIH 4.2 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V 4
Maximum Low-Level Input Voltage VIL 0.5 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 2.0 V 4
Maximum Low-Level Input Voltage VIL 0.9 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 3.0 V 4
Maximum Low-Level Input Voltage VIL 1.35 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 4.5 V 4
Maximum Low-Level Input Voltage VIL 1.8 V Vout = 0.1 V or VCC, 0.1 V; /Iout/ ≤ 20 µA; VCC = 6.0 V 4
Minimum High-Level Output Voltage VOH 1.9 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V 4
Minimum High-Level Output Voltage VOH 4.4 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 4.5 V 4
Minimum High-Level Output Voltage VOH 5.9 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 6.0 V 4
Minimum High-Level Output Voltage VOH 2.2 V Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V 4
Minimum High-Level Output Voltage VOH 3.7 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC = 4.5 V 4
Minimum High-Level Output Voltage VOH 5.2 V Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; VCC = 6.0 V 4
Maximum Low-Level Output Voltage VOL 0.1 V Vin = VIH or VIL; /Iout/ ≤ 20 µA; VCC = 2.0 V 4
Maximum Low-Level Output Voltage VOL 0.26 V Vin = VIH or VIL; /Iout/ ≤ 2.4 mA; VCC = 3.0 V 4
Maximum Low-Level Output Voltage VOL 0.33 V Vin = VIH or VIL; /Iout/ ≤ 4.0 mA; VCC = 4.5 V 4
Maximum Low-Level Output Voltage VOL 0.4 V Vin = VIH or VIL; /Iout/ ≤ 5.2 mA; VCC = 6.0 V 4
Maximum Input Leakage Current Iin -1 1 µA Vin = VCC or GND; VCC = 6.0 V 4
Maximum Quiescent Supply Current (per Package) ICC 160 µA Vin = VCC or GND; Iout = 0 µA; VCC = 6.0 V 4
Maximum Propagation Delay, Input A to Output Y tPLH, tPHL 205 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 1 and 4); VCC = 2.0 V 4
Maximum Propagation Delay, Input A to Output Y tPLH, tPHL 165 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 1 and 4); VCC = 3.0 V 4
Maximum Propagation Delay, Input A to Output Y tPLH, tPHL 41 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 1 and 4); VCC = 4.5 V 4
Maximum Propagation Delay, Input A to Output Y tPLH, tPHL 35 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 1 and 4); VCC = 6.0 V 4
Maximum Propagation Delay, CS1 to Output Y tPLH, tPHL 165 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 2.0 V 4
Maximum Propagation Delay, CS1 to Output Y tPLH, tPHL 125 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 3.0 V 4
Maximum Propagation Delay, CS1 to Output Y tPLH, tPHL 33 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 4.5 V 4
Maximum Propagation Delay, CS1 to Output Y tPLH, tPHL 28 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 6.0 V 4
Maximum Propagation Delay, CS2 or CS3 to Output Y tPLH, tPHL 180 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 3 and 4); VCC = 2.0 V 4
Maximum Propagation Delay, CS2 or CS3 to Output Y tPLH, tPHL 150 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 3 and 4); VCC = 3.0 V 4
Maximum Propagation Delay, CS2 or CS3 to Output Y tPLH, tPHL 36 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 3 and 4); VCC = 4.5 V 4
Maximum Propagation Delay, CS2 or CS3 to Output Y tPLH, tPHL 31 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 3 and 4); VCC = 6.0 V 4
Maximum Output Transition Time, Any Output tTLH, tTHL 110 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 2.0 V 4
Maximum Output Transition Time, Any Output tTLH, tTHL 55 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 3.0 V 4
Maximum Output Transition Time, Any Output tTLH, tTHL 22 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 4.5 V 4
Maximum Output Transition Time, Any Output tTLH, tTHL 19 ns CL = 50 pF, input tr = tf = 6.0 ns (Figures 2 and 4); VCC = 6.0 V 4
Maximum Input Capacitance Cin 10 pF 4

CAD (KiCad official)

  • Symbol: NLV74HC138ADR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: nlv74hc138adr2g-etched.step / nlv74hc138adr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nlv74hc138adr2g.step / nlv74hc138adr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (10 pp, sha256 3fb79c20ec75b50f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF