NL27WZ04DFT2G

{
 "schema": "adom.pads/1",
 "slug": "nl27wz04dft2g",
 "footprint": "SOT-363_SC-70-6",
 "generated_from": {
  "footprint": "SOT-363_SC-70-6@sha256:0659d885e00b7869",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -0.8375,
   -0.65
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-363_SC-70-6@sha256:0659d885e00b7869"
 },
 "pad_count": 6,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5",
  "6"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "IN A1",
   "type": "input",
   "description": "Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "GND",
   "type": "power_in",
   "description": "Ground reference (0 V). Maximum DC ground current per pin is ±100 mA.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "IN A2",
   "type": "input",
   "description": "Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "OUT Y2",
   "type": "output",
   "description": "Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 µF decoupling to GND.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    0.8375,
    -0.65
   ],
   "rot": 0.0,
   "size": [
    1.025,
    0.35
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "OUT Y1",
   "type": "output",
   "description": "Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-363_SC-70-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}