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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs nl27wz04dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
nl27wz04dft2g-etched.fit.json nl27wz04dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl27wz04dft2g-etched.glb nl27wz04dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl27wz04dft2g-etched.step nl27wz04dft2g: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
nl27wz04dft2g.glb Publish 0.1.0 · Ray
nl27wz04dft2g.kicad_mod Publish 0.1.0 · Ray
nl27wz04dft2g.kicad_sym Publish 0.1.0 · Ray
nl27wz04dft2g.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
nl27wz04dft2g.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json nl27wz04dft2g: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md nl27wz04dft2g: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

NL27WZ04DFT2G

onsemi · Inverters · SC-70-6(SOT-363)

NL27WZ04DFT2G from onsemi, in a SC-70-6(SOT-363). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN A1 input Logic input to inverter 1. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC.
2 GND power_in Ground reference (0 V). Maximum DC ground current per pin is ±100 mA.
3 IN A2 input Logic input to inverter 2. LVTTL/LVCMOS compatible, high-impedance input; VIH = 0.7·VCC (0.75·VCC below 2.3 V VCC), VIL = 0.3·VCC. Tolerates up to 5.5 V regardless of VCC.
4 OUT Y2 output Inverted logic output of inverter 2 (Y2 = /A2). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load.
5 VCC power_in Positive supply. Operating range 1.65 V to 5.5 V (1.5 V min for data retention only). Recommend local 0.1 µF decoupling to GND.
6 OUT Y1 output Inverted logic output of inverter 1 (Y1 = /A1). Push-pull CMOS output with 24 mA balanced sink/source capability; VOH ≈ VCC−0.1 V and VOL ≈ 0.1 V at 100 µA load.

Key specifications

Parameter Value
Manufacturer onsemi
Package SC-70-6(SOT-363)
Category Logic
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • NL27WZ04DFT2GDFT1G
  • NL27WZ04DFT2G
  • NL27WZ04DFT2GDTT1G

CAD (KiCad official)

  • Symbol: NL27WZ04DFT2G
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6(SOT-363) (KiCad packages3D, STEP)
  • 3D model files: nl27wz04dft2g-etched.step / nl27wz04dft2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nl27wz04dft2g.step / nl27wz04dft2g.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
nl27wz04dft2g.step 99 KB You want the bare part, or you mark your own boards.
nl27wz04dft2g-etched.step 2.0 MB You want the part with NL27WZ04DFT2G already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 510 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (6 pp, sha256 28312bb40d206466, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF