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NCV5700DR2G

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onsemi Gate Drive ICs, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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NCV5700DR2G

onsemi · Gate Drive ICs · SO-16

NCV5700DR2G from onsemi, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input allows additional gating of VOH and VOL and can turn the driver output off independently of the microcontroller input; the absolute maximum VEN−GND range is −0.3 V to 5.5 V.
2 VIN power_in Input signal controlling the output with signal inversion from VIN to VOH/VOL; VIN is internally clamped to 5.5 V, has a 1 MΩ pull-up to keep the output low without an input, and requires a minimum pulse width before VOH/VOL activate.
3 VREF power_in 5 V reference generated within the driver, brought out for external bypassing and for powering low-bias circuits such as digital isolators; the recommended capacitance is 100 nF and the reference output current is specified at 20 mA maximum.
4 FLT output Active-low fault output that tells the controller the driver has detected a fault and deactivated the output; absolute maximum FLT sink current is 20 mA and source current is 25 mA.
5 GNDA power_in Convenient connection point for bypass capacitors (e.g. REF) on the left side of the package.
6 NC unconnected Pin not internally connected.
7 RSVD unconnected Reserved pin; no connection is allowed.
8 NC unconnected Pin not internally connected.
9 DESAT input Input for detecting IGBT desaturation; a capacitor on this pin sets a programmable blanking delay every ON cycle before a DESAT fault is processed, and the absolute maximum DESAT voltage is −0.3 V to VCC + 0.3 V.
10 VCC power_in Positive bias supply for the driver with an operating range from UVLO to the maximum, requiring a good quality bypass capacitor to GND placed close to the pins; the absolute maximum VCC−GND is 22 V.
11 VOH output Driver high output providing the drive voltage and source current to the IGBT gate; the absolute maximum VOH−GND is VCC + 0.3 V.
12 VOL output Driver low output providing the drive voltage and sink current to the IGBT gate, actively pulled low during start-up and fault conditions.
13 GND power_in Connect to the IGBT emitter with a short trace; all power-pin bypass capacitors should be referenced to this pin and kept a short distance from it.
14 VEE power_in Negative bias pin allowing VOL to go to a negative voltage during the OFF state (negative supply range −15 V to 0 V); a good quality bypass capacitor to GND is required, and if no negative voltage is used this pin must be connected to GND.
15 VEEA power_in Analog version of the VEE pin for signal trace connections, internally connected to VEE.
16 CLAMP bidirectional Active Miller clamp pin that clamps the IGBT gate during the off period to protect it from parasitic turn-on; it must be tied directly to the IGBT gate with minimum trace length.

Key specifications

Parameter Value
Manufacturer onsemi
Package SO-16
Category Power Management ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Power Supply (Vmax) VCC−VEE (Vmax) 0 36 V 4
Positive Power Supply VCC−GND -0.3 22 V 4
Negative Power Supply VEE−GND -18 0.3 V 4
Input Voltage VIN−GND -0.3 5.5 V 4
Enable Voltage VEN−GND -0.3 5.5 V 4
FLT Current Sink IFLT−SINK 20 mA 4
FLT Current Source IFLT−SRC 25 mA 4
Power Dissipation PD 900 mW SO−16 package 4
Maximum Junction Temperature TJ(max) 150 °C 4
Storage Temperature Range TSTG -65 150 °C 4
Differential Power Supply (Vmax) operating VCC−VEE (Vmax) 30 V 4
Positive Power Supply VCC UVLO VCC UVLO 20 V 4
Negative Power Supply VEE -15 0 V 4
Input Voltage VIN 0 5 V 4
Enable Voltage VEN 0 5 V 4
Input Pulse Width ton 40 ns 4
Ambient Temperature TA -40 125 °C 4
Input Threshold, High-state (Logic 1) VIN−H1 4.3 V Pulse−Width = 150 ns, VEN = 5 V 5
Input Threshold, Low-state (Logic 0) VIN−L1 1.2 V Pulse−Width = 150 ns, VEN = 5 V 5
Input No-state-change range VIN−NC 0.75 3.7 V No state change, Pulse−Width = 150 ns, VEN = 5 V 5
Enable Threshold, High-state VEN−H 4.3 V VIN = 0 V 5
Enable Threshold, Low-state VEN−L 0.75 V VIN = 0 V 5
Input/Enable Internal Pull-Up Resistance to VREF RIN−H/REN−H 1 M 5
Input Pulse-Width, No Response at the Output ton−min1 30 ns No Response at the Output; voltage thresholds consistent with input specs 5
Input Pulse-Width, Guaranteed Response at the Output ton−min2 10 ns Guaranteed Response at the Output; voltage thresholds consistent with input specs 5
FLT Threshold Voltage, Low State VFLT−L 0.5 1 V IFLT−SINK = 15 mA 5
FLT Threshold Voltage, High State VFLT−H 12 13.9 V IFLT−SRC = 20 mA 5
Output Low State (VOL1) VOL1 0.1 0.2 V Isink = 200 mA, TA = 25°C 5
Output Low State (VOL2) VOL2 0.2 0.5 V Isink = 200 mA, TA = −40°C to 125°C 5
Output Low State (VOL3) VOL3 0.8 1.2 V Isink = 1.0 A, TA = 25°C 5
Output High State (VOH1) VOH1 14.5 14.8 V Isrc = 200 mA, TA = 25°C 5
Output High State (VOH2) VOH2 14.2 14.7 V Isrc = 200 mA, TA = −40°C to 125°C 5
Output High State (VOH3) VOH3 13.8 14.1 V Isrc = 1.0 A, TA = 25°C 5
Peak Driver Current, Sink (VO = 13 V) IPK−snk1 6.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 13 V 5
Peak Driver Current, Sink (near Miller Plateau) IPK−snk2 6.1 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 5
Peak Driver Current, Source (VO = −5 V) IPK−src1 7.8 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = −5 V 5
Peak Driver Current, Source (near Miller Plateau) IPK−src2 4 A RG = 0.1, VCC = 15 V, VEE = −8 V, VO = 9 V (near Miller Plateau) 5
Turn-on Delay tpd−on 45 56 75 ns Negative input pulse width = 10 s 5
Turn-off Delay tpd−off 45 63 75 ns Positive input pulse width = 10 s 5
Propagation Delay Distortion (tpd−on − tpd−off), TA = −40°C to 125°C tdistort2 -25 25 ns For input or output pulse width > 150 ns, TA = −40°C to 125°C 5
Rise Time trise 9.2 ns Cload = 1.0 nF 5
Fall Time tfall 7.9 ns Cload = 1.0 nF 5
Delay from FLT under UVLO/TSD to VOL td1−OUT 9 12 15 s 6
Delay from DESAT to VOL td2−OUT 220 ns 6
Delay from UVLO/TSD to FLT td3−FLT 7.3 s 6
Clamp Voltage, TA = 25°C Vclamp 1.2 1.4 V Isink = 500 mA, TA = 25°C 6
Clamp Voltage, TA = −40°C to 125°C Vclamp 2.2 V Isink = 500 mA, TA = −40°C to 125°C 6
Clamp Activation Threshold VMC−THR 1.8 2 2.2 V 6
DESAT Threshold Voltage VDESAT−THR 6 6.35 7 V 6
Blanking Charge Current IDESAT−CHG 0.2 0.24 0.28 mA 6
UVLO Startup Voltage VUVLO−OUT−ON 13.2 13.5 13.8 V 6
UVLO Disable Voltage VUVLO−OUT−OFF 12.2 12.5 12.8 V 6
UVLO Hysteresis VUVLO−HYST 1 V 6
Voltage Reference VREF 4.85 5 5.15 V IREF = 10 mA 6
Recommended Capacitance CVREF 100 nF VREF bypass, at least 6
Current Drawn from VCC, Standby ICC−SB 0.9 1.5 mA VCC = 15 V, no load on output, FLT, VREF 6
Current Drawn from VEE, Standby IEE−SB -0.2 -0.14 mA VEE = −10 V, no load on output, FLT, VREF 6
Thermal Shutdown Temperature TSD 188 °C Values based on design and/or characterization (Note 7) 6
Thermal Resistance, Junction-to-Air (SOIC-16) RθJA 145 °C/W Copper area 100 mm2 (0.16 in2), 1 oz copper, FR4 PCB (Note 5) 4

CAD (KiCad official)

  • Symbol: NCV5700DR2G
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)
  • 3D model files: ncv5700dr2g-etched.step / ncv5700dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ncv5700dr2g.step / ncv5700dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (19 pp, sha256 945a07307c48a515, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF